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Merged
merged 58 commits into from
Dec 10, 2019
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acomodi
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@acomodi acomodi commented Oct 2, 2019

Description

This PR is a followup of #941. The main purpose is to add the equivalent sites placement. In fact, if the architecture specifies that a pb_type can be placed in two or more different physical tiles, the placer can now use those tiles.

Related Issue

#513

Motivation and Context

The placer should be able to find better solutions whenever there is a clustered block that could be placed in all the possible physical tiles that can be used.

This change neatly separates the domains of the packer and placer. This means that the placer becomes more flexible in finding solutions that are currently unfeasible and strictly dependent on the packer outcomes.

How Has This Been Tested?

There is a WIP regression test, which needs to be fixed.

Types of changes

  • Bug fix (change which fixes an issue)
  • New feature (change which adds functionality)
  • Breaking change (fix or feature that would cause existing functionality to change)

Checklist:

  • My change requires a change to the documentation
  • I have updated the documentation accordingly
  • I have added tests to cover my changes
  • All new and existing tests passed

@probot-autolabeler probot-autolabeler bot added lang-cpp C/C++ code libarchfpga Library for handling FPGA Architecture descriptions VPR VPR FPGA Placement & Routing Tool labels Oct 2, 2019
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acomodi commented Oct 2, 2019

@kmurray @litghost FYI

I have added the WIP tag as the regression tests will fail due to the need of updating the architecture files. In fact now also the pin directs have to be provided to each equivalent site.

I believe though that the major effort is completed and this PR can go through a first review step.

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acomodi commented Oct 2, 2019

I have just tried to manually update the archs and got the following error on all the regression tests:

...
Warning 24: in check_rr_node: RR node: 631 type: OPIN location: (1,1) pin: 102 pin_name: clb.cout[0] has no out-going edges.
Warning 25: in check_rr_node: RR node: 632 type: OPIN location: (1,1) pin: 103 pin_name: clb.cout[1] has no out-going edges.
Warning 26: in check_rr_node: RR node: 1573 type: OPIN location: (3,1) pin: 102 pin_name: clb.cout[0] has no out-going edges.
Warning 27: in check_rr_node: RR node: 1574 type: OPIN location: (3,1) pin: 103 pin_name: clb.cout[1] has no out-going edges.
Warning 28: in check_rr_graph: fringe node 24 IPIN at (0,1) has no fanin.                                          
         This is possible on a fringe node based on low Fc_out, N, and certain lengths.                            
## Build routing resource graph took 0.00 seconds (max_rss 23.3 MiB, delta_rss +0.0 MiB)                           
  RR Graph Nodes: 2676                                                                                             
  RR Graph Edges: 5593                                                                                             
Confirming router algorithm: TIMING_DRIVEN.                                                                        
---- ------ ------- ---- ------- ------- ------- ----------------- --------------- -------- ---------- ---------- ---------- ---------- --------
Iter   Time    pres  BBs    Heap  Re-Rtd  Re-Rtd Overused RR Nodes      Wirelength      CPD       sTNS       sWNS       hTNS       hWNS Est Succ
      (sec)     fac Updt    push    Nets   Conns                                       (ns)       (ns)       (ns)       (ns)       (ns)     Iter
---- ------ ------- ---- ------- ------- ------- ----------------- --------------- -------- ---------- ---------- ---------- ---------- --------
vtr/vpr/src/route/route_timing.cpp:1044 timing_driven_route_net: Assertion 'route_ctx.rr_node_route_inf[rt_root->inode].occ() <= device_ctx.rr_nodes[rt_root->inode].capacity()' failed (SOURCE should never be congested).
Aborted (core dumped) 

I guess there is something wrong with the rr_nodes

@probot-autolabeler probot-autolabeler bot added the infra Project Infrastructure label Oct 3, 2019
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acomodi commented Oct 3, 2019

@kmurray I have solved the issue with routing. When assigning the physical pin index from the directs mapping I did not consider the capacity, hence there was an overusage of node causing the failure.

I have temporarily added the upgrade_arch.sh script step in Travis CI to check the regression tests (f050da8).

CI should turn green, at least on the strong_regression_tests which I have locally tested.

@acomodi acomodi mentioned this pull request Oct 4, 2019
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acomodi commented Oct 4, 2019

@kmurray FYI, I have fixed the issues to let CI go green

@acomodi acomodi force-pushed the equivalent-sites branch 2 times, most recently from 55c5ea7 to b6f0a0b Compare October 7, 2019 11:33
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acomodi commented Oct 7, 2019

@kmurray with this commit I am trying to get rid of the necessity of calling the pin_physical_index() method to retrieve the physical index associated with a block.
I have thought to move the information on what logical pin is associated with a specific tile elsewhere, instead of having it embedded in the clustering information.

@acomodi acomodi force-pushed the equivalent-sites branch 2 times, most recently from 8092c17 to 2411d95 Compare October 16, 2019 10:43
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acomodi commented Oct 16, 2019

@kmurray, @vaughnbetz Ping.
This PR can now use equivalent sites in more complex situations as done in this Symbiflow PR: f4pga/f4pga-arch-defs#1072.

This still needs some work, but IMO it is ready for review.

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acomodi commented Oct 16, 2019

TODO

  • More intelligent initial placement;
  • SINK/SOURCE to IPIN/OPIN issue;
  • Add documentation

@probot-autolabeler probot-autolabeler bot added the docs Documentation label Oct 17, 2019
@acomodi acomodi force-pushed the equivalent-sites branch 3 times, most recently from 2dc250d to 0062735 Compare October 21, 2019 13:15
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acomodi commented Oct 23, 2019

@kmurray @vaughnbetz I have added an initial small regression test to check the correct behavior of the equivalent tiles placement.

CI went red when compiling with gcc-9 with the following output error:

[  1%] Linking CXX executable read_arch
lto1: fatal error: bytecode stream in file ‘../libvtrutil/libvtrutil.a’ generated with LTO version 8.0 instead of the expected 8.1
compilation terminated.
lto-wrapper: fatal error: /usr/bin/g++-9 returned 1 exit status
compilation terminated.
/usr/bin/ld: lto-wrapper failed
collect2: error: ld returned 1 exit status
make[3]: *** [libs/libarchfpga/read_arch] Error 1
make[2]: *** [libs/libarchfpga/CMakeFiles/read_arch.dir/all] Error 2
make[1]: *** [all] Error 2
make: *** [all] Error 2

Is this an infrastructure fault?

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mithro commented Oct 23, 2019

Build failure is probably caused by the build cache? If @kmurray can delete the cache it should work...

Signed-off-by: Alessandro Comodi <[email protected]>
Also solved draw.cpp issue

Signed-off-by: Alessandro Comodi <[email protected]>
Signed-off-by: Alessandro Comodi <[email protected]>
…fferences

This change enables a sorting of the logical block and physical tiles
equivalent counterpart lists based on the differences in the number of pins.

This ordering allows to select the "best" corresponding candidate of a
logical/physical type when there is the need to access its data.

This also allows to not rely on the `pick_random_type` function

Signed-off-by: Alessandro Comodi <[email protected]>
equivalent: add compatibility check in is_legal_swap

Signed-off-by: Alessandro Comodi <[email protected]>
added tutorial for using equivalent sites.

Signed-off-by: Alessandro Comodi <[email protected]>
Deleted usage of the following utility functions as their functionality
was not required anymore:
    - `int find_clb_pb_pin(ClusterBlockId clb, int clb_pin);`
    - `int find_pb_pin_clb_pin(ClusterBlockId clb, int pb_pin);`

In fact they were returning different values depending on the
`nets_and_pins_synced_to_z_coordinate` boolean which is currently
unused.

Added comments to newly introduced utility functions and changed name
to have higher understendability

Signed-off-by: Alessandro Comodi <[email protected]>
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acomodi commented Dec 10, 2019

@kmurray Thanks for the review.

One note about the new changes:
I have deleted the usage of the following utility functions as their functionality was not required anymore:
- int find_clb_pb_pin(ClusterBlockId clb, int clb_pin);
- int find_pb_pin_clb_pin(ClusterBlockId clb, int pb_pin);

In fact they were returning different values depending on the nets_and_pins_synced_to_z_coordinate boolean which is currently unused.

@kmurray kmurray merged commit cb2043b into verilog-to-routing:master Dec 10, 2019
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kmurray commented Dec 10, 2019

Great, thanks @acomodi !

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