equivalent: addressed review comments

Deleted usage of the following utility functions as their functionality
was not required anymore:
    - `int find_clb_pb_pin(ClusterBlockId clb, int clb_pin);`
    - `int find_pb_pin_clb_pin(ClusterBlockId clb, int pb_pin);`

In fact they were returning different values depending on the
`nets_and_pins_synced_to_z_coordinate` boolean which is currently
unused.

Added comments to newly introduced utility functions and changed name
to have higher understendability

Signed-off-by: Alessandro Comodi <[email protected]>

Author: acomodi

vpr/src/base/read_route.cpp

@@ -378,7 +378,7 @@ static void process_global_blocks(std::ifstream& fp, ClusterNetId inet, const ch
                           x, y, place_ctx.block_locs[bnum].loc.x, place_ctx.block_locs[bnum].loc.y);
             }
 
-            int pin_index = net_pin_tile_index(inet, pin_counter);
+            int pin_index = net_pin_to_tile_pin_index(inet, pin_counter);
             if (physical_tile_type(bnum)->pin_class[pin_index] != atoi(tokens[7].c_str())) {
                 vpr_throw(VPR_ERROR_ROUTE, filename, lineno,
                           "The pin class %d of %lu net does not match given ",

vpr/src/base/vpr_types.h

@@ -625,13 +625,11 @@ struct t_place_region {
  * x: x-coordinate
  * y: y-coordinate
  * z: occupancy coordinate
- * is_fixed: true if this block's position is fixed by the user and shouldn't be moved during annealing
- * nets_and_pins_synced_to_z_coordinate: true if the associated clb's pins have been synced to the z location (i.e. after placement) */
+ * is_fixed: true if this block's position is fixed by the user and shouldn't be moved during annealing */
 struct t_block_loc {
     t_pl_loc loc;
 
     bool is_fixed = false;
-    bool nets_and_pins_synced_to_z_coordinate = false;
 };
 
 /* Stores the clustered blocks placed at a particular grid location */

vpr/src/place/place.cpp

@@ -1390,7 +1390,7 @@ static void update_net_bb(const ClusterNetId net,
         }
     } else {
         //For large nets, update bounding box incrementally
-        int iblk_pin = pin_tile_index(blk_pin);
+        int iblk_pin = tile_pin_index(blk_pin);
 
         t_physical_tile_type_ptr blk_type = physical_tile_type(blk);
         int pin_width_offset = blk_type->pin_width_offset[iblk_pin];
@@ -1841,7 +1841,7 @@ static void get_bb_from_scratch(ClusterNetId net_id, t_bb* coords, t_bb* num_on_
     auto& grid = device_ctx.grid;
 
     ClusterBlockId bnum = cluster_ctx.clb_nlist.net_driver_block(net_id);
-    pnum = net_pin_tile_index(net_id, 0);
+    pnum = net_pin_to_tile_pin_index(net_id, 0);
     VTR_ASSERT(pnum >= 0);
     x = place_ctx.block_locs[bnum].loc.x + physical_tile_type(bnum)->pin_width_offset[pnum];
     y = place_ctx.block_locs[bnum].loc.y + physical_tile_type(bnum)->pin_height_offset[pnum];
@@ -1860,7 +1860,7 @@ static void get_bb_from_scratch(ClusterNetId net_id, t_bb* coords, t_bb* num_on_
 
     for (auto pin_id : cluster_ctx.clb_nlist.net_sinks(net_id)) {
         bnum = cluster_ctx.clb_nlist.pin_block(pin_id);
-        pnum = pin_tile_index(pin_id);
+        pnum = tile_pin_index(pin_id);
         x = place_ctx.block_locs[bnum].loc.x + physical_tile_type(bnum)->pin_width_offset[pnum];
         y = place_ctx.block_locs[bnum].loc.y + physical_tile_type(bnum)->pin_height_offset[pnum];
 
@@ -2000,7 +2000,7 @@ static void get_non_updateable_bb(ClusterNetId net_id, t_bb* bb_coord_new) {
     auto& device_ctx = g_vpr_ctx.device();
 
     ClusterBlockId bnum = cluster_ctx.clb_nlist.net_driver_block(net_id);
-    pnum = net_pin_tile_index(net_id, 0);
+    pnum = net_pin_to_tile_pin_index(net_id, 0);
     x = place_ctx.block_locs[bnum].loc.x + physical_tile_type(bnum)->pin_width_offset[pnum];
     y = place_ctx.block_locs[bnum].loc.y + physical_tile_type(bnum)->pin_height_offset[pnum];
 
@@ -2011,7 +2011,7 @@ static void get_non_updateable_bb(ClusterNetId net_id, t_bb* bb_coord_new) {
 
     for (auto pin_id : cluster_ctx.clb_nlist.net_sinks(net_id)) {
         bnum = cluster_ctx.clb_nlist.pin_block(pin_id);
-        pnum = pin_tile_index(pin_id);
+        pnum = tile_pin_index(pin_id);
         x = place_ctx.block_locs[bnum].loc.x + physical_tile_type(bnum)->pin_width_offset[pnum];
         y = place_ctx.block_locs[bnum].loc.y + physical_tile_type(bnum)->pin_height_offset[pnum];
 

vpr/src/route/check_route.cpp

@@ -190,7 +190,7 @@ static void check_sink(int inode, ClusterNetId net_id, bool* pin_done) {
         unsigned int ipin = 1;
         for (auto pin_id : cluster_ctx.clb_nlist.net_sinks(net_id)) {
             if (cluster_ctx.clb_nlist.pin_block(pin_id) == bnum) {
-                int pin_index = pin_tile_index(pin_id);
+                int pin_index = tile_pin_index(pin_id);
                 int iclass = type->pin_class[pin_index];
                 if (iclass == ptc_num) {
                     /* Could connect to same pin class on the same clb more than once.  Only   *
@@ -245,7 +245,7 @@ static void check_source(int inode, ClusterNetId net_id) {
     }
 
     //Get the driver pin's index in the block
-    auto physical_pin = net_pin_tile_index(net_id, 0);
+    auto physical_pin = net_pin_to_tile_pin_index(net_id, 0);
 
     int iclass = type->pin_class[physical_pin];
 

vpr/src/route/route_common.cpp

@@ -1054,7 +1054,7 @@ static vtr::vector<ClusterNetId, std::vector<int>> load_net_rr_terminals(const t
             /* In the routing graph, each (x, y) location has unique pins on it
              * so when there is capacity, blocks are packed and their pin numbers
              * are offset to get their actual rr_node */
-            int phys_pin = pin_tile_index(pin_id);
+            int phys_pin = tile_pin_index(pin_id);
 
             int iclass = type->pin_class[phys_pin];
 
@@ -1538,7 +1538,7 @@ void print_route(FILE* fp, const vtr::vector<ClusterNetId, t_traceback>& traceba
 
             for (auto pin_id : cluster_ctx.clb_nlist.net_pins(net_id)) {
                 ClusterBlockId block_id = cluster_ctx.clb_nlist.pin_block(pin_id);
-                int pin_index = pin_tile_index(pin_id);
+                int pin_index = tile_pin_index(pin_id);
                 int iclass = physical_tile_type(block_id)->pin_class[pin_index];
 
                 fprintf(fp, "Block %s (#%zu) at (%d,%d), Pin class %d.\n",

vpr/src/timing/clb_delay_calc.inl

@@ -10,13 +10,11 @@ inline ClbDelayCalc::ClbDelayCalc()
     : intra_lb_pb_pin_lookup_(g_vpr_ctx.device().logical_block_types) {}
 
 inline float ClbDelayCalc::clb_input_to_internal_sink_delay(const ClusterBlockId block_id, const int pin_index, int internal_sink_pin, DelayType delay_type) const {
-    int pb_ipin = find_clb_pb_pin(block_id, pin_index);
-    return trace_delay(block_id, pb_ipin, internal_sink_pin, delay_type);
+    return trace_delay(block_id, pin_index, internal_sink_pin, delay_type);
 }
 
 inline float ClbDelayCalc::internal_src_to_clb_output_delay(const ClusterBlockId block_id, const int pin_index, int internal_src_pin, DelayType delay_type) const {
-    int pb_opin = find_clb_pb_pin(block_id, pin_index);
-    return trace_delay(block_id, internal_src_pin, pb_opin, delay_type);
+    return trace_delay(block_id, internal_src_pin, pin_index, delay_type);
 }
 
 inline float ClbDelayCalc::internal_src_to_internal_sink_delay(const ClusterBlockId clb, int internal_src_pin, int internal_sink_pin, DelayType delay_type) const {

vpr/src/util/vpr_utils.cpp

@@ -505,67 +505,13 @@ std::tuple<ClusterNetId, int, int> find_pb_route_clb_input_net_pin(ClusterBlockI
         return std::make_tuple(ClusterNetId::INVALID(), -1, -1);
     }
 
-    //To account for capacity > 1 blocks we need to convert the pb_pin to the clb pin
-    int clb_pin = find_pb_pin_clb_pin(clb, curr_pb_pin_id);
-    VTR_ASSERT(clb_pin >= 0);
-
-    //clb_pin should be a top-level CLB input
-    ClusterNetId clb_net_idx = cluster_ctx.clb_nlist.block_net(clb, clb_pin);
-    int clb_net_pin_idx = cluster_ctx.clb_nlist.block_pin_net_index(clb, clb_pin);
+    //curr_pb_pin should be a top-level CLB input
+    ClusterNetId clb_net_idx = cluster_ctx.clb_nlist.block_net(clb, curr_pb_pin_id);
+    int clb_net_pin_idx = cluster_ctx.clb_nlist.block_pin_net_index(clb, curr_pb_pin_id);
     VTR_ASSERT(clb_net_idx != ClusterNetId::INVALID());
     VTR_ASSERT(clb_net_pin_idx >= 0);
 
-    return std::tuple<ClusterNetId, int, int>(clb_net_idx, clb_pin, clb_net_pin_idx);
-}
-
-//Return the pb pin index corresponding to the pin clb_pin on block clb
-// Given a clb_pin index on a this function will return the corresponding
-// pin index on the pb_type (accounting for the possible z-coordinate offset).
-int find_clb_pb_pin(ClusterBlockId clb, int clb_pin) {
-    auto& place_ctx = g_vpr_ctx.placement();
-
-    auto type = physical_tile_type(clb);
-    VTR_ASSERT_MSG(clb_pin < type->num_pins, "Must be a valid top-level pin");
-
-    int pb_pin = -1;
-    if (place_ctx.block_locs[clb].nets_and_pins_synced_to_z_coordinate) {
-        //Pins have been offset by z-coordinate, need to remove offset
-
-        VTR_ASSERT(type->num_pins % type->capacity == 0);
-        int num_basic_block_pins = type->num_pins / type->capacity;
-        /* Logical location and physical location is offset by z * max_num_block_pins */
-
-        pb_pin = clb_pin - place_ctx.block_locs[clb].loc.z * num_basic_block_pins;
-    } else {
-        pb_pin = clb_pin;
-    }
-
-    VTR_ASSERT(pb_pin >= 0);
-
-    return pb_pin;
-}
-
-//Inverse of find_clb_pb_pin()
-int find_pb_pin_clb_pin(ClusterBlockId clb, int pb_pin) {
-    auto& place_ctx = g_vpr_ctx.placement();
-
-    auto type = physical_tile_type(clb);
-
-    int clb_pin = -1;
-    if (place_ctx.block_locs[clb].nets_and_pins_synced_to_z_coordinate) {
-        //Pins have been offset by z-coordinate, need to remove offset
-        VTR_ASSERT(type->num_pins % type->capacity == 0);
-        int num_basic_block_pins = type->num_pins / type->capacity;
-        /* Logical location and physical location is offset by z * max_num_block_pins */
-
-        clb_pin = pb_pin + place_ctx.block_locs[clb].loc.z * num_basic_block_pins;
-    } else {
-        //No offset
-        clb_pin = pb_pin;
-    }
-    VTR_ASSERT(clb_pin >= 0);
-
-    return clb_pin;
+    return std::tuple<ClusterNetId, int, int>(clb_net_idx, curr_pb_pin_id, clb_net_pin_idx);
 }
 
 bool is_clb_external_pin(ClusterBlockId blk_id, int pb_pin_id) {
@@ -2108,7 +2054,6 @@ void place_sync_external_block_connections(ClusterBlockId iblk) {
     auto& cluster_ctx = g_vpr_ctx.clustering();
     auto& clb_nlist = cluster_ctx.clb_nlist;
     auto& place_ctx = g_vpr_ctx.mutable_placement();
-    VTR_ASSERT_MSG(place_ctx.block_locs[iblk].nets_and_pins_synced_to_z_coordinate == false, "Block net and pins must not be already synced");
 
     auto physical_tile = physical_tile_type(iblk);
     auto logical_block = clb_nlist.block_type(iblk);
@@ -2130,9 +2075,6 @@ void place_sync_external_block_connections(ClusterBlockId iblk) {
             place_ctx.physical_pins.insert(pin, new_physical_pin_index);
         }
     }
-
-    //Mark the block as synced
-    //place_ctx.block_locs[iblk].nets_and_pins_synced_to_z_coordinate = true;
 }
 
 int get_max_num_pins(t_logical_block_type_ptr logical_block) {
@@ -2210,16 +2152,16 @@ int get_physical_pin(t_physical_tile_type_ptr physical_tile,
     return result->second.pin;
 }
 
-int net_pin_tile_index(const ClusterNetId net_id, int net_pin_index) {
+int net_pin_to_tile_pin_index(const ClusterNetId net_id, int net_pin_index) {
     auto& cluster_ctx = g_vpr_ctx.clustering();
 
     // Get the logical pin index of pin within it's logical block type
     auto pin_id = cluster_ctx.clb_nlist.net_pin(net_id, net_pin_index);
 
-    return pin_tile_index(pin_id);
+    return tile_pin_index(pin_id);
 }
 
-int pin_tile_index(const ClusterPinId pin) {
+int tile_pin_index(const ClusterPinId pin) {
     auto& place_ctx = g_vpr_ctx.placement();
 
     return place_ctx.physical_pins[pin];

vpr/src/util/vpr_utils.h

@@ -85,22 +85,6 @@ std::vector<AtomPinId> find_clb_pin_sink_atom_pins(ClusterBlockId clb, int logic
 
 std::tuple<ClusterNetId, int, int> find_pb_route_clb_input_net_pin(ClusterBlockId clb, int sink_pb_route_id);
 
-//Return the pb pin index corresponding to the pin clb_pin on block clb,
-//acounting for the effect of 'z' position > 0.
-//
-//  Note that a CLB pin index does not (neccessarily) map directly to the pb_route index representing the first stage
-//  of internal routing in the block, since a block may have capacity > 1 (e.g. IOs)
-//
-//  In the clustered netlist blocks with capacity > 1 may have their 'z' position > 0, and their clb pin indicies offset
-//  by the number of pins on the type (c.f. post_place_sync()).
-//
-//  This offset is not mirrored in the t_pb or pb graph, so we need to recover the basic pin index before processing
-//  further -- which is what this function does.
-int find_clb_pb_pin(ClusterBlockId clb, int clb_pin);
-
-//Return the clb_pin corresponding to the pb_pin on the specified block
-int find_pb_pin_clb_pin(ClusterBlockId clb, int pb_pin);
-
 //Returns the port matching name within pb_gnode
 const t_port* find_pb_graph_port(const t_pb_graph_node* pb_gnode, std::string port_name);
 
@@ -180,8 +164,11 @@ int get_physical_pin(t_physical_tile_type_ptr physical_tile,
                      t_logical_block_type_ptr logical_block,
                      int pin);
 
-int net_pin_tile_index(const ClusterNetId net_id, int net_pin_index);
-int pin_tile_index(const ClusterPinId pin);
+//Returns the physical pin of the tile, related to the given ClusterNedId, and the net pin index
+int net_pin_to_tile_pin_index(const ClusterNetId net_id, int net_pin_index);
+
+//Returns the physical pin of the tile, related to the given ClusterPinId
+int tile_pin_index(const ClusterPinId pin);
 
 int max_pins_per_grid_tile();