Code

Equivalent sites#988

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kmurray merged 58 commits intoverilog-to-routing:masterverilog-to-routing/vtr-verilog-to-routing:masterfrom

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Dec 10, 2019

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Commits on Dec 10, 2019

• place: WIP added equivalent sites strong regression test

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• place: added equivalent sites placement capability

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• place: added placement priority and check direct pin mappings

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• place: fix equivalent placement issues

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• place: added post-placement resources utilization log

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• place: fixed issue with place_macro output echo file

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• place: fixed warnings for potentially uninitialized variable

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• place: solved capacity issue in route_common

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• place: fix empty type seg fault

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• place: corrected num_pins assertion in clustered netlist

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• place: added few comments and removed compile warning

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• place: solved valgrind memory leak

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• place: use vtr::rand only when needed

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• arch: updated architecture files to have direct pin mapping

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• Improve error message when port cannot be found.

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• Avoid segfault when a tile is not present in grid.

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• equivalent: added checks for equivalent sites pins

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• equivalent: patch to have different tile - block names

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• equivalent: added VPR_THROW when no corresponding type is found

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• equivalent: added check that each pb_type has at least one equivalent tile

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• equivalent: add referenced veriable in for loop

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• equivalent: clb_directs should affect phy tiles and not log blocks

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• equivalent: skip empty tile

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• equivalent: avoid segfaults

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• equivalent: added bimap to store pin mappings between tile and block

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• equivalent: fixed bug in clb_directs

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• equivalent: using physical_tiles instead of logical_block

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• equivalent: added Documentation

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• place: move initial placement in separate file

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• equivalent: delete physical_tile_type(t_logical_block_type) function

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• equivalent: updated regression test (WIP)

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• equivalent: fix potential segfaults

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• equivalent: fixed physical-logical pin bug

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• equivalent: use logical-physical pin mappings

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• Fix failing assertion.

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• equivalent: fix warning in draw.cpp

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• WIP: testbench

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• equivalent: avoid using logical_block_type() func

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• equivalent: fixing auto-sizing of FPGA device with equivalent tiles

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• equivalent: fixed initial regression test

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• equivalent: adopting direct/custom pin_mapping

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• Revert "arch: updated architecture files to have direct pin mapping"

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• upgrade_arch: add pin_mapping attribute to equivalent_sites

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• equivalent: equivalent regression test with custom pin_mapping

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• equivalent: remove placement priority attribute from architectures

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• equivalent: sorting blocks and pl_macros in initial_placement

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• equivalent: initial placement sorts only if equivalent tiles are present

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• place: rename locations alloc/load functions during initial placement

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• equivalent: change phy/log_pin to physical/logical_pin

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• equivalent: added in-code comments

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• equivalent: remove need of equivalent_sites_names

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• equivalent: fixed example architecture.xml in docs

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• equivalent: reorder physical/logical equivalent tiles based on pin differences

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• equivalent: use logical_block_types in compressed grid locations

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• equivalent: check mutual phy/log type compatibility when swapping

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• equivalent: delete pin_physical_index from clustered netlist

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• docs: added/modified equivalent sites documentation

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• equivalent: addressed review comments

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