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arch: updated architecture files to have direct pin mapping
Signed-off-by: Alessandro Comodi <[email protected]>
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203 files changed

+5043
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‎libs/libarchfpga/arch/mult_luts_arch.xml

Lines changed: 24 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -54,7 +54,11 @@
5454
<tiles>
5555
<tile name="io" capacity="7">
5656
<equivalent_sites>
57-
<site pb_type="io"/>
57+
<site pb_type="io">
58+
<direct from="io.outpad" to="io.outpad"/>
59+
<direct from="io.inpad" to="io.inpad"/>
60+
<direct from="io.clock" to="io.clock"/>
61+
</site>
5862
</equivalent_sites>
5963
<input name="outpad" num_pins="1" equivalent="none"/>
6064
<output name="inpad" num_pins="1"/>
@@ -69,7 +73,11 @@
6973
</tile>
7074
<tile name="clb">
7175
<equivalent_sites>
72-
<site pb_type="clb"/>
76+
<site pb_type="clb">
77+
<direct from="clb.I" to="clb.I"/>
78+
<direct from="clb.O" to="clb.O"/>
79+
<direct from="clb.clk" to="clb.clk"/>
80+
</site>
7381
</equivalent_sites>
7482
<input name="I" num_pins="56" equivalent="full"/>
7583
<output name="O" num_pins="16"/>
@@ -79,7 +87,15 @@
7987
</tile>
8088
<tile name="memory" height="4">
8189
<equivalent_sites>
82-
<site pb_type="memory"/>
90+
<site pb_type="memory">
91+
<direct from="memory.addr1" to="memory.addr1"/>
92+
<direct from="memory.addr2" to="memory.addr2"/>
93+
<direct from="memory.data" to="memory.data"/>
94+
<direct from="memory.we1" to="memory.we1"/>
95+
<direct from="memory.we2" to="memory.we2"/>
96+
<direct from="memory.out" to="memory.out"/>
97+
<direct from="memory.clk" to="memory.clk"/>
98+
</site>
8399
</equivalent_sites>
84100
<input name="addr1" num_pins="16"/>
85101
<input name="addr2" num_pins="16"/>
@@ -93,7 +109,11 @@
93109
</tile>
94110
<tile name="mult_36" height="3">
95111
<equivalent_sites>
96-
<site pb_type="mult_36"/>
112+
<site pb_type="mult_36">
113+
<direct from="mult_36.a" to="mult_36.a"/>
114+
<direct from="mult_36.b" to="mult_36.b"/>
115+
<direct from="mult_36.out" to="mult_36.out"/>
116+
</site>
97117
</equivalent_sites>
98118
<input name="a" num_pins="36"/>
99119
<input name="b" num_pins="36"/>

‎libs/libarchfpga/arch/sample_arch.xml

Lines changed: 24 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -135,7 +135,11 @@
135135
<tiles>
136136
<tile name="io" capacity="8">
137137
<equivalent_sites>
138-
<site pb_type="io"/>
138+
<site pb_type="io">
139+
<direct from="io.outpad" to="io.outpad"/>
140+
<direct from="io.inpad" to="io.inpad"/>
141+
<direct from="io.clock" to="io.clock"/>
142+
</site>
139143
</equivalent_sites>
140144
<input name="outpad" num_pins="1"/>
141145
<output name="inpad" num_pins="1"/>
@@ -150,7 +154,11 @@
150154
</tile>
151155
<tile name="clb">
152156
<equivalent_sites>
153-
<site pb_type="clb"/>
157+
<site pb_type="clb">
158+
<direct from="clb.I" to="clb.I"/>
159+
<direct from="clb.O" to="clb.O"/>
160+
<direct from="clb.clk" to="clb.clk"/>
161+
</site>
154162
</equivalent_sites>
155163
<input name="I" num_pins="33" equivalent="full"/>
156164
<output name="O" num_pins="20" equivalent="none"/>
@@ -160,7 +168,11 @@
160168
</tile>
161169
<tile name="mult_36" height="4">
162170
<equivalent_sites>
163-
<site pb_type="mult_36"/>
171+
<site pb_type="mult_36">
172+
<direct from="mult_36.a" to="mult_36.a"/>
173+
<direct from="mult_36.b" to="mult_36.b"/>
174+
<direct from="mult_36.out" to="mult_36.out"/>
175+
</site>
164176
</equivalent_sites>
165177
<input name="a" num_pins="36"/>
166178
<input name="b" num_pins="36"/>
@@ -170,7 +182,15 @@
170182
</tile>
171183
<tile name="memory" height="6">
172184
<equivalent_sites>
173-
<site pb_type="memory"/>
185+
<site pb_type="memory">
186+
<direct from="memory.addr1" to="memory.addr1"/>
187+
<direct from="memory.addr2" to="memory.addr2"/>
188+
<direct from="memory.data" to="memory.data"/>
189+
<direct from="memory.we1" to="memory.we1"/>
190+
<direct from="memory.we2" to="memory.we2"/>
191+
<direct from="memory.out" to="memory.out"/>
192+
<direct from="memory.clk" to="memory.clk"/>
193+
</site>
174194
</equivalent_sites>
175195
<input name="addr1" num_pins="15"/>
176196
<input name="addr2" num_pins="15"/>

‎utils/fasm/test/test_fasm_arch.xml

Lines changed: 10 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,11 @@
33
<tiles>
44
<tile name="io" capacity="8">
55
<equivalent_sites>
6-
<site pb_type="io"/>
6+
<site pb_type="io">
7+
<direct from="io.outpad" to="io.outpad"/>
8+
<direct from="io.inpad" to="io.inpad"/>
9+
<direct from="io.clock" to="io.clock"/>
10+
</site>
711
</equivalent_sites>
812
<input name="outpad" num_pins="1"/>
913
<output name="inpad" num_pins="1"/>
@@ -18,7 +22,11 @@
1822
</tile>
1923
<tile name="clb">
2024
<equivalent_sites>
21-
<site pb_type="clb"/>
25+
<site pb_type="clb">
26+
<direct from="clb.I" to="clb.I"/>
27+
<direct from="clb.O" to="clb.O"/>
28+
<direct from="clb.clk" to="clb.clk"/>
29+
</site>
2230
</equivalent_sites>
2331
<input name="I" num_pins="33" equivalent="full"/>
2432
<output name="O" num_pins="20" equivalent="none"/>

‎vpr/test/test_read_arch_metadata.xml

Lines changed: 10 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,11 @@
33
<tiles>
44
<tile name="io" capacity="8">
55
<equivalent_sites>
6-
<site pb_type="io"/>
6+
<site pb_type="io">
7+
<direct from="io.outpad" to="io.outpad"/>
8+
<direct from="io.inpad" to="io.inpad"/>
9+
<direct from="io.clock" to="io.clock"/>
10+
</site>
711
</equivalent_sites>
812
<input name="outpad" num_pins="1"/>
913
<output name="inpad" num_pins="1"/>
@@ -18,7 +22,11 @@
1822
</tile>
1923
<tile name="clb">
2024
<equivalent_sites>
21-
<site pb_type="clb"/>
25+
<site pb_type="clb">
26+
<direct from="clb.I" to="clb.I"/>
27+
<direct from="clb.O" to="clb.O"/>
28+
<direct from="clb.clk" to="clb.clk"/>
29+
</site>
2230
</equivalent_sites>
2331
<input name="I" num_pins="33" equivalent="full"/>
2432
<output name="O" num_pins="20" equivalent="none"/>

‎vtr_flow/arch/bidir/k4_n4_v7_bidir.xml

Lines changed: 10 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -26,7 +26,11 @@ Architecture based off Stratix IV
2626
<tiles>
2727
<tile name="io" capacity="4">
2828
<equivalent_sites>
29-
<site pb_type="io"/>
29+
<site pb_type="io">
30+
<direct from="io.outpad" to="io.outpad"/>
31+
<direct from="io.inpad" to="io.inpad"/>
32+
<direct from="io.clock" to="io.clock"/>
33+
</site>
3034
</equivalent_sites>
3135
<input name="outpad" num_pins="1"/>
3236
<output name="inpad" num_pins="1"/>
@@ -41,7 +45,11 @@ Architecture based off Stratix IV
4145
</tile>
4246
<tile name="clb">
4347
<equivalent_sites>
44-
<site pb_type="clb"/>
48+
<site pb_type="clb">
49+
<direct from="clb.I" to="clb.I"/>
50+
<direct from="clb.O" to="clb.O"/>
51+
<direct from="clb.clk" to="clb.clk"/>
52+
</site>
4553
</equivalent_sites>
4654
<input name="I" num_pins="10" equivalent="full"/>
4755
<output name="O" num_pins="4" equivalent="instance"/>

‎vtr_flow/arch/bidir/k4_n4_v7_bidir_pass_gate.xml

Lines changed: 10 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -26,7 +26,11 @@ Architecture based off Stratix IV
2626
<tiles>
2727
<tile name="io" capacity="4">
2828
<equivalent_sites>
29-
<site pb_type="io"/>
29+
<site pb_type="io">
30+
<direct from="io.outpad" to="io.outpad"/>
31+
<direct from="io.inpad" to="io.inpad"/>
32+
<direct from="io.clock" to="io.clock"/>
33+
</site>
3034
</equivalent_sites>
3135
<input name="outpad" num_pins="1"/>
3236
<output name="inpad" num_pins="1"/>
@@ -41,7 +45,11 @@ Architecture based off Stratix IV
4145
</tile>
4246
<tile name="clb">
4347
<equivalent_sites>
44-
<site pb_type="clb"/>
48+
<site pb_type="clb">
49+
<direct from="clb.I" to="clb.I"/>
50+
<direct from="clb.O" to="clb.O"/>
51+
<direct from="clb.clk" to="clb.clk"/>
52+
</site>
4553
</equivalent_sites>
4654
<input name="I" num_pins="10" equivalent="full"/>
4755
<output name="O" num_pins="4" equivalent="instance"/>

‎vtr_flow/arch/bidir/k4_n4_v7_l1_bidir.xml

Lines changed: 10 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -26,7 +26,11 @@ Architecture based off Stratix IV
2626
<tiles>
2727
<tile name="io" capacity="4">
2828
<equivalent_sites>
29-
<site pb_type="io"/>
29+
<site pb_type="io">
30+
<direct from="io.outpad" to="io.outpad"/>
31+
<direct from="io.inpad" to="io.inpad"/>
32+
<direct from="io.clock" to="io.clock"/>
33+
</site>
3034
</equivalent_sites>
3135
<input name="outpad" num_pins="1"/>
3236
<output name="inpad" num_pins="1"/>
@@ -41,7 +45,11 @@ Architecture based off Stratix IV
4145
</tile>
4246
<tile name="clb">
4347
<equivalent_sites>
44-
<site pb_type="clb"/>
48+
<site pb_type="clb">
49+
<direct from="clb.I" to="clb.I"/>
50+
<direct from="clb.O" to="clb.O"/>
51+
<direct from="clb.clk" to="clb.clk"/>
52+
</site>
4553
</equivalent_sites>
4654
<input name="I" num_pins="10" equivalent="full"/>
4755
<output name="O" num_pins="4" equivalent="instance"/>

‎vtr_flow/arch/bidir/k4_n4_v7_longline_bidir.xml

Lines changed: 10 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -26,7 +26,11 @@ Architecture based off Stratix IV
2626
<tiles>
2727
<tile name="io" capacity="4">
2828
<equivalent_sites>
29-
<site pb_type="io"/>
29+
<site pb_type="io">
30+
<direct from="io.outpad" to="io.outpad"/>
31+
<direct from="io.inpad" to="io.inpad"/>
32+
<direct from="io.clock" to="io.clock"/>
33+
</site>
3034
</equivalent_sites>
3135
<input name="outpad" num_pins="1"/>
3236
<output name="inpad" num_pins="1"/>
@@ -41,7 +45,11 @@ Architecture based off Stratix IV
4145
</tile>
4246
<tile name="clb">
4347
<equivalent_sites>
44-
<site pb_type="clb"/>
48+
<site pb_type="clb">
49+
<direct from="clb.I" to="clb.I"/>
50+
<direct from="clb.O" to="clb.O"/>
51+
<direct from="clb.clk" to="clb.clk"/>
52+
</site>
4553
</equivalent_sites>
4654
<input name="I" num_pins="10" equivalent="full"/>
4755
<output name="O" num_pins="4" equivalent="instance"/>

‎vtr_flow/arch/common/arch.xml

Lines changed: 10 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -14,7 +14,12 @@
1414
<tiles>
1515
<tile name="ff_tile">
1616
<equivalent_sites>
17-
<site pb_type="ff_tile"/>
17+
<site pb_type="ff_tile">
18+
<direct from="ff_tile.in" to="ff_tile.in"/>
19+
<direct from="ff_tile.out" to="ff_tile.out"/>
20+
<direct from="ff_tile.clk" to="ff_tile.clk"/>
21+
<direct from="ff_tile.cen" to="ff_tile.cen"/>
22+
</site>
1823
</equivalent_sites>
1924
<input name="in" num_pins="4"/>
2025
<output name="out" num_pins="4"/>
@@ -30,7 +35,10 @@
3035
</tile>
3136
<tile name="io_tile">
3237
<equivalent_sites>
33-
<site pb_type="io_tile"/>
38+
<site pb_type="io_tile">
39+
<direct from="io_tile.in" to="io_tile.in"/>
40+
<direct from="io_tile.out" to="io_tile.out"/>
41+
</site>
3442
</equivalent_sites>
3543
<input name="in" num_pins="1"/>
3644
<output name="out" num_pins="1"/>

‎vtr_flow/arch/complex_switch/k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml

Lines changed: 31 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -69,7 +69,11 @@
6969
<tiles>
7070
<tile name="io" capacity="8">
7171
<equivalent_sites>
72-
<site pb_type="io"/>
72+
<site pb_type="io">
73+
<direct from="io.outpad" to="io.outpad"/>
74+
<direct from="io.inpad" to="io.inpad"/>
75+
<direct from="io.clock" to="io.clock"/>
76+
</site>
7377
</equivalent_sites>
7478
<input name="outpad" num_pins="1"/>
7579
<output name="inpad" num_pins="1"/>
@@ -88,7 +92,18 @@
8892
</tile>
8993
<tile name="clb" area="3900">
9094
<equivalent_sites>
91-
<site pb_type="clb"/>
95+
<site pb_type="clb">
96+
<direct from="clb.I0" to="clb.I0"/>
97+
<direct from="clb.I1" to="clb.I1"/>
98+
<direct from="clb.I2" to="clb.I2"/>
99+
<direct from="clb.I3" to="clb.I3"/>
100+
<direct from="clb.I4" to="clb.I4"/>
101+
<direct from="clb.I5" to="clb.I5"/>
102+
<direct from="clb.I6" to="clb.I6"/>
103+
<direct from="clb.I7" to="clb.I7"/>
104+
<direct from="clb.O" to="clb.O"/>
105+
<direct from="clb.clk" to="clb.clk"/>
106+
</site>
92107
</equivalent_sites>
93108
<input name="I0" num_pins="4" equivalent="full"/>
94109
<input name="I1" num_pins="4" equivalent="full"/>
@@ -116,7 +131,11 @@
116131
</tile>
117132
<tile name="mult_36" height="4" area="118800">
118133
<equivalent_sites>
119-
<site pb_type="mult_36"/>
134+
<site pb_type="mult_36">
135+
<direct from="mult_36.a" to="mult_36.a"/>
136+
<direct from="mult_36.b" to="mult_36.b"/>
137+
<direct from="mult_36.out" to="mult_36.out"/>
138+
</site>
120139
</equivalent_sites>
121140
<input name="a" num_pins="36"/>
122141
<input name="b" num_pins="36"/>
@@ -130,7 +149,15 @@
130149
</tile>
131150
<tile name="memory" height="4" area="82748">
132151
<equivalent_sites>
133-
<site pb_type="memory"/>
152+
<site pb_type="memory">
153+
<direct from="memory.addr1" to="memory.addr1"/>
154+
<direct from="memory.addr2" to="memory.addr2"/>
155+
<direct from="memory.data" to="memory.data"/>
156+
<direct from="memory.we1" to="memory.we1"/>
157+
<direct from="memory.we2" to="memory.we2"/>
158+
<direct from="memory.out" to="memory.out"/>
159+
<direct from="memory.clk" to="memory.clk"/>
160+
</site>
134161
</equivalent_sites>
135162
<input name="addr1" num_pins="14"/>
136163
<input name="addr2" num_pins="14"/>

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