Route 3d #2330

saaramahmoudi · 2023-05-31T20:07:28Z

Description

In this PR, I have modified the RRGraph generation to support more than one available die (e.g., 3D FPGA). I have changed the tag in arch file to describe an attribute named "layer_offset". The layer_offset for each physical pin will specify which layer this pin is connected to. Hence, an IPIN/OPIN located at layer 0 can be connected to the upper die with layer_offset=1.

Since we have more than one die available, we want to give the user the ability to specify which die(dice) has global routing resources (wire segment, switch blocks, ..). Hence, a new optional attribute is defined for the tag called "has_routing_resources" and it can hint the RRGraph to build or ignore the routing resource graph for each die.

Related Issue

This PR is entirely dependent on place_3d, shouldn't be merged before the place_3d PR.

Types of changes

Bug fix (change which fixes an issue)
New feature (change which adds functionality)
Breaking change (fix or feature that would cause existing functionality to change)

Checklist:

My change requires a change to the documentation
I have updated the documentation accordingly
I have added tests to cover my changes
All new and existing tests passed

…cess functions to work with it

…ed by 3D-FPGAs

…signment for custom pinlocations

…cture functionality

…verilog-to-routing into inter_die_communication

…rilog-to-routing into inter_die_communication

…verilog-to-routing into inter_die_communication

…rilog-to-routing into inter_die_communication

…upport 3d rrgraph

…_find

…n 3d but should work for 2d arch files

…verilog-to-routing into inter_die_communication

…support

…ch physical type

…ayer_offset itself

…in_layer_offset

…verilog-to-routing into inter_die_communication

… to calculate it

…rent layer

saaramahmoudi · 2023-06-30T19:55:18Z

@amin1377

VPR Command:
$VTR_ROOT/vtr_flow/arch/multi_die/3d_k4_N4_90nm.xml $VTR_ROOT/vtr_flow/benchmarks/blif/4/alu4.blif --device "FPGA3D" --route_chan_width 40

Problem:
When only OPINs are connected across different layers, compute delta delay takes a lot of time.

saaramahmoudi · 2023-06-30T23:18:26Z

@amin1377

For S-IV with all IPINs and OPINs connectd to other layers: vtr_flow/arch/multi_die/stratixiv_arch.timing.xml
For S-IV with only OPINs connected to other layers: vtr_flow/arch/multi_die/stratixiv_arch.timing_OPINs.xml

vpr/src/route/router_lookahead_map.cpp

vpr/src/route/rr_graph.cpp

vpr/src/route/rr_graph2.cpp

libs/libarchfpga/src/physical_types_util.h

saaramahmoudi · 2023-07-04T04:03:26Z

@amin1377 I have attached koios architecture files under arch/multi_die.

Both OPINS and IPINS: vtr_flow/arch/multi_die/k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml

Only OPINS: vtr_flow/arch/multi_die/k6FracN10LB_mem20K_complexDSP_customSB_22nm_OPINs.xml

…o other layers

…to-routing/vtr-verilog-to-routing into inter_die_communication

saaramahmoudi · 2023-07-13T14:16:53Z

Here is the branch result for 2d benchmarks (Titan and VTR) to double check that my changes didn't degrade the QoR for 2d designs. The branch is compared to current master branch.
QoR check

saaramahmoudi · 2023-07-17T17:38:14Z

@vaughnbetz ready to merge.

saaramahmoudi added 29 commits May 17, 2023 13:40

add an extra tag for layer offset in pinlocation tag and modified pro…

732081b

…cess functions to work with it

added a pin_layer_offset to t_physical_tile_type data structure

cf993ad

debug: VTR_ASSERT was flipped for layer_offset

58a121e

ProcessPinLocations function updated to work with layer_offset requir…

f671707

…ed by 3D-FPGAs

minor debugging, initialize the pin assignment with layer_offset

e28de59

LoadPinLoc updated to work with layer offset derived from pin_loc->as…

aaf7ec2

…signment for custom pinlocations

parsing architecture file using pinlocations layer_offset

5e24125

added layer_offset to 3d architecture file to confirm parsing archite…

09f9675

…cture functionality

Merge branch 'place_3d' of https://github.com/verilog-to-routing/vtr-…

e5d5545

…verilog-to-routing into inter_die_communication

completed LoadPinLoc function with layer_offset

dec2998

Merge branch 'place_3d' of https://github.com/verilog-to-routing/vtr-…

29880da

…verilog-to-routing into inter_die_communication

Merge branch 'master' of https://github.com/verilog-to-routing/vtr-ve…

3a26065

…rilog-to-routing into inter_die_communication

Merge branch 'place_3d' of https://github.com/verilog-to-routing/vtr-…

261e9dc

…verilog-to-routing into inter_die_communication

Merge branch 'master' of https://github.com/verilog-to-routing/vtr-ve…

0766883

…rilog-to-routing into inter_die_communication

modified the pin to track connection to account for layer_number to s…

7bd4605

…upport 3d rrgraph

modified alloc_and_load_track_to_pin_lookup to account for layer_num

ee5e622

fixed track to pin map dumping in the echo file

914f436

changed the build_rr_* functions to pass the correct layer to rr_node…

a131f45

…_find

fix all compiler issues and runtime problem, rr graph is incomplete i…

c202ee1

…n 3d but should work for 2d arch files

Merge branch 'place_3d' of https://github.com/verilog-to-routing/vtr-…

4023854

…verilog-to-routing into inter_die_communication

updated get_undir_opin_connections

118fa1f

tracks can find IPINS on the other layers to connect to them

3fc1354

Merge branch 'place_3d' of https://github.com/verilog-to-routing/vtr-…

01fd70c

…verilog-to-routing into inter_die_communication

updated pin_to_track and track_to_pin data structure to work with 3D …

b2ecf09

…support

removed hardcoding layer numbers and add type_layer to account for ea…

aa791c5

…ch physical type

updated alloc_and_load_pin_to_track_map to calculate type_layer and l…

e4728e4

…ayer_offset itself

changed alloc_and_load_track_to_pin_lookup arguments to account for p…

fdd0cea

…in_layer_offset

make format

7b4e136

Merge branch 'place_3d' of https://github.com/verilog-to-routing/vtr-…

5ed3948

…verilog-to-routing into inter_die_communication

saaramahmoudi changed the title ~~[WP] route_3d~~ [WIP] Route 3d May 31, 2023

saaramahmoudi added 3 commits June 30, 2023 13:30

Merge branch 'master' into inter_die_communication

07c46bb

removed physical_type_layer from device_ctx and add a helper function…

fa998a4

… to calculate it

updated architecture 3d_k4_N4_90nm.xml to connect only OPINS to diffe…

6ba16ce

…rent layer

saaramahmoudi added 4 commits June 30, 2023 17:24

applied PR suggestion from VB

cc62834

make format

e992891

3d S4 arch with only OPINS connected

0935ca2

Merge branch 'master' into inter_die_communication

4e1f1a2

Merge branch 'master' into inter_die_communication

c07ce4f

amin1377 reviewed Jul 3, 2023

View reviewed changes

saaramahmoudi added 2 commits July 3, 2023 23:42

koios architecture with OPINS/IPINS connected to other layers

b5067ab

add arch file for koios when only OPINS are connected to other layers

63bc65a

saaramahmoudi added 11 commits July 4, 2023 13:11

factor out wrap around in rr_graph

3512591

fix lookahead_map to work with inter_prog for each layer

08e5d56

add support for inter dice switch while reading rr graph

2955943

debug: rr graph was generated incorrectly with only OPINs connected t…

8a28f6e

…o other layers

make format

ef52ac1

fixed compiler warning related to null pointer dereference

f3bc909

Merge branch 'master' into inter_die_communication

fd2ef48

debug: pin to track map matrix size updated

ec82c03

Merge branch 'inter_die_communication' of https://github.com/verilog-…

146021e

…to-routing/vtr-verilog-to-routing into inter_die_communication

resolved conflits with flat router test

b264d40

Architecture added for 3d Graphic

72e4b39

print switch type info in arch.echo

2330613

vaughnbetz merged commit 5a6249a into master Jul 17, 2023

vaughnbetz deleted the inter_die_communication branch July 17, 2023 17:45

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Description

Related Issue

Types of changes

Checklist:

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