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Jul 17, 2023
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732081b
add an extra tag for layer offset in pinlocation tag and modified pro…
saaramahmoudi May 17, 2023
cf993ad
added a pin_layer_offset to t_physical_tile_type data structure
saaramahmoudi May 17, 2023
58a121e
debug: VTR_ASSERT was flipped for layer_offset
saaramahmoudi May 17, 2023
f671707
ProcessPinLocations function updated to work with layer_offset requir…
saaramahmoudi May 18, 2023
e28de59
minor debugging, initialize the pin assignment with layer_offset
saaramahmoudi May 18, 2023
aaf7ec2
LoadPinLoc updated to work with layer offset derived from pin_loc->as…
saaramahmoudi May 18, 2023
5e24125
parsing architecture file using pinlocations layer_offset
saaramahmoudi May 18, 2023
09f9675
added layer_offset to 3d architecture file to confirm parsing archite…
saaramahmoudi May 18, 2023
e5d5545
Merge branch 'place_3d' of https://github.com/verilog-to-routing/vtr-…
saaramahmoudi May 18, 2023
dec2998
completed LoadPinLoc function with layer_offset
saaramahmoudi May 18, 2023
29880da
Merge branch 'place_3d' of https://github.com/verilog-to-routing/vtr-…
saaramahmoudi May 19, 2023
3a26065
Merge branch 'master' of https://github.com/verilog-to-routing/vtr-ve…
saaramahmoudi May 25, 2023
261e9dc
Merge branch 'place_3d' of https://github.com/verilog-to-routing/vtr-…
saaramahmoudi May 25, 2023
0766883
Merge branch 'master' of https://github.com/verilog-to-routing/vtr-ve…
saaramahmoudi May 26, 2023
7bd4605
modified the pin to track connection to account for layer_number to s…
saaramahmoudi May 26, 2023
ee5e622
modified alloc_and_load_track_to_pin_lookup to account for layer_num
saaramahmoudi May 26, 2023
914f436
fixed track to pin map dumping in the echo file
saaramahmoudi May 26, 2023
a131f45
changed the build_rr_* functions to pass the correct layer to rr_node…
saaramahmoudi May 27, 2023
c202ee1
fix all compiler issues and runtime problem, rr graph is incomplete i…
saaramahmoudi May 27, 2023
4023854
Merge branch 'place_3d' of https://github.com/verilog-to-routing/vtr-…
saaramahmoudi May 27, 2023
118fa1f
updated get_undir_opin_connections
saaramahmoudi May 29, 2023
3fc1354
tracks can find IPINS on the other layers to connect to them
saaramahmoudi May 30, 2023
01fd70c
Merge branch 'place_3d' of https://github.com/verilog-to-routing/vtr-…
saaramahmoudi May 30, 2023
b2ecf09
updated pin_to_track and track_to_pin data structure to work with 3D …
saaramahmoudi May 31, 2023
aa791c5
removed hardcoding layer numbers and add type_layer to account for ea…
saaramahmoudi May 31, 2023
e4728e4
updated alloc_and_load_pin_to_track_map to calculate type_layer and l…
saaramahmoudi May 31, 2023
fdd0cea
changed alloc_and_load_track_to_pin_lookup arguments to account for p…
saaramahmoudi May 31, 2023
7b4e136
make format
saaramahmoudi May 31, 2023
5ed3948
Merge branch 'place_3d' of https://github.com/verilog-to-routing/vtr-…
saaramahmoudi May 31, 2023
207d2e0
filled physical_type_layer in device_grid.cpp and moved it to device_…
saaramahmoudi May 31, 2023
0fcb403
Merge branch 'master' into inter_die_communication
saaramahmoudi May 31, 2023
8339cba
Merge branch 'place_3d' of https://github.com/verilog-to-routing/vtr-…
saaramahmoudi May 31, 2023
050e4ca
fixed some hardcoding of layer_offset
saaramahmoudi May 31, 2023
9bbda8d
Merge branch 'inter_die_communication' of https://github.com/verilog-…
saaramahmoudi May 31, 2023
d077d2f
make format
saaramahmoudi Jun 1, 2023
9bc75f4
fixed the seg fault causing by hardcoding the layer_num
saaramahmoudi Jun 1, 2023
dbb9932
Merge branch 'master' into inter_die_communication
saaramahmoudi Jun 6, 2023
6449dea
added a new tag for architecture file to specify which FPGA die requi…
saaramahmoudi Jun 6, 2023
9682ab8
Merge branch 'place_3d' of https://github.com/verilog-to-routing/vtr-…
saaramahmoudi Jun 6, 2023
9f4b401
avoid building extra routing resources on base die when there is only…
saaramahmoudi Jun 6, 2023
3a45917
minor bug in parsing the arch file for global resource routing
saaramahmoudi Jun 8, 2023
e796be1
make format
saaramahmoudi Jun 8, 2023
9a45936
fixed lookahead warning for dice without global routing resources
saaramahmoudi Jun 8, 2023
de1125f
added a child tag for track to ipin switch, updated corresponding dat…
saaramahmoudi Jun 15, 2023
0844bda
changed switch id for multi-die connections
saaramahmoudi Jun 15, 2023
90bc0e2
added edge delay for opin to track connection
saaramahmoudi Jun 15, 2023
7941fa3
added a simple arch for test multi-die FPGAs
saaramahmoudi Jun 15, 2023
7e8ca99
make format
saaramahmoudi Jun 15, 2023
aa037ba
opins/ipins in each layer can be connected to tracks within the same …
saaramahmoudi Jun 16, 2023
d8704a9
opins in layer 0 for 2-dice FPGA fabric can be connected to both laye…
saaramahmoudi Jun 16, 2023
54f065e
make format
saaramahmoudi Jun 16, 2023
302917c
debug: in 2d cases had some edge duplication since pin_layer and laye…
saaramahmoudi Jun 20, 2023
7b3d1c0
simplify arch file to wrap around layer_offset in case of being invalid
saaramahmoudi Jun 22, 2023
f4a9c71
resolved conflicts with master branch after removing route tree
saaramahmoudi Jun 22, 2023
e70a168
make format
saaramahmoudi Jun 22, 2023
59cbee5
debug: fixed memory corruption in rr_graph
saaramahmoudi Jun 22, 2023
b76fa10
debug: layer_offset set correctly if subtile has more than 1 capacity
saaramahmoudi Jun 22, 2023
7082ac3
Merge branch 'master' into inter_die_communication
saaramahmoudi Jun 27, 2023
c464514
Merge branch 'master' into inter_die_communication
saaramahmoudi Jun 29, 2023
00bc1cb
added a helper function to determine whether pin is connected to anot…
saaramahmoudi Jun 29, 2023
7908c2d
added S4 multi-die arch file
saaramahmoudi Jun 30, 2023
07c46bb
Merge branch 'master' into inter_die_communication
saaramahmoudi Jun 30, 2023
fa998a4
removed physical_type_layer from device_ctx and add a helper function…
saaramahmoudi Jun 30, 2023
6ba16ce
updated architecture 3d_k4_N4_90nm.xml to connect only OPINS to diffe…
saaramahmoudi Jun 30, 2023
cc62834
applied PR suggestion from VB
saaramahmoudi Jun 30, 2023
e992891
make format
saaramahmoudi Jun 30, 2023
0935ca2
3d S4 arch with only OPINS connected
saaramahmoudi Jun 30, 2023
4e1f1a2
Merge branch 'master' into inter_die_communication
saaramahmoudi Jun 30, 2023
c07ce4f
Merge branch 'master' into inter_die_communication
saaramahmoudi Jul 1, 2023
b5067ab
koios architecture with OPINS/IPINS connected to other layers
saaramahmoudi Jul 4, 2023
63bc65a
add arch file for koios when only OPINS are connected to other layers
saaramahmoudi Jul 4, 2023
3512591
factor out wrap around in rr_graph
saaramahmoudi Jul 4, 2023
08e5d56
fix lookahead_map to work with inter_prog for each layer
saaramahmoudi Jul 4, 2023
2955943
add support for inter dice switch while reading rr graph
saaramahmoudi Jul 4, 2023
8a28f6e
debug: rr graph was generated incorrectly with only OPINs connected t…
saaramahmoudi Jul 5, 2023
ef52ac1
make format
saaramahmoudi Jul 6, 2023
f3bc909
fixed compiler warning related to null pointer dereference
saaramahmoudi Jul 6, 2023
fd2ef48
Merge branch 'master' into inter_die_communication
saaramahmoudi Jul 10, 2023
ec82c03
debug: pin to track map matrix size updated
saaramahmoudi Jul 11, 2023
146021e
Merge branch 'inter_die_communication' of https://github.com/verilog-…
saaramahmoudi Jul 11, 2023
b264d40
resolved conflits with flat router test
saaramahmoudi Jul 11, 2023
72e4b39
Architecture added for 3d Graphic
saaramahmoudi Jul 11, 2023
2330613
print switch type info in arch.echo
saaramahmoudi Jul 13, 2023
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4 changes: 3 additions & 1 deletion libs/libarchfpga/src/echo_arch.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -231,7 +231,8 @@ void PrintArchInfo(FILE* Echo, const t_arch* arch) {
break;
}

fprintf(Echo, "\tInput Connect Block Switch Name: %s\n", arch->ipin_cblock_switch_name.c_str());
//TODO: SM must update the echo file to echo inter_die connections
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Don't forget these to do's: should do them now or file an issue to remember them.

fprintf(Echo, "\tInput Connect Block Switch Name: %s\n", arch->ipin_cblock_switch_name[0].c_str());

fprintf(Echo, "*************************************************\n\n");
//Switch list
Expand Down Expand Up @@ -282,6 +283,7 @@ void PrintArchInfo(FILE* Echo, const t_arch* arch) {
//wire_switch == arch_opin_switch
fprintf(Echo, "\t\t\t\ttype unidir mux_name %s\n",
arch->Switches[seg.arch_wire_switch].name.c_str());
//TODO: SM: must update echo file for wire switch between multi-die FPGAs
} else { //Should be bidir
fprintf(Echo, "\t\t\t\ttype bidir wire_switch %s arch_opin_switch %s\n",
arch->Switches[seg.arch_wire_switch].name.c_str(),
Expand Down
30 changes: 24 additions & 6 deletions libs/libarchfpga/src/physical_types.h
Original file line number Diff line number Diff line change
Expand Up @@ -575,6 +575,9 @@ constexpr int DEFAULT_SWITCH = -2;
* pinloc: Is set to true if a given pin exists on a certain position of a
* block. Derived from pin_location_distribution/pin_loc_assignments
*
* pin_layer_offset/pin_width_offset/pin_height_offset: offset from the anchor point
* of the block type in the x,y, and layer (dice number) direction.
*
* pin_location_distribution: The pin distribution type
* num_pin_loc_assignments: The number of strings within each pin_loc_assignments
* pin_loc_assignments: The strings for a custom pin location distribution.
Expand Down Expand Up @@ -609,17 +612,18 @@ constexpr int DEFAULT_SWITCH = -2;
* logical_tile_index: index of the corresponding logical block type
*
* In general, the physical tile is a placeable physical resource on the FPGA device,
* and it is allowed to contain an heterogeneous set of logical blocks (pb_types).
* and it is allowed to contain a heterogeneous set of logical blocks (pb_types).
*
* Each physical tile must specify at least one sub tile, that is a physical location
* on the sub tiles stacks. This means that a physical tile occupies an (x, y) location on the grid,
* and it has at least one sub tile slot that allows for a placement within the (x, y) location.
*
* Therefore, to identify the location of a logical block within the device grid, we need to
* specify three different coordinates:
* specify four different coordinates:
* - x : horizontal coordinate
* - y : vertical coordinate
* - sub tile : location within the sub tile stack at an (x, y) physical location
* -layer_num : the layer that block is located at. In case of a single die, layer_num is 0.
*
* A physical tile is heterogeneous as it allows the placement of different kinds of logical blocks within,
* that can share the same (x, y) placement location.
Expand Down Expand Up @@ -650,6 +654,7 @@ struct t_physical_tile_type {
int primitive_class_starting_idx = -1;
std::unordered_map<int, t_class> primitive_class_inf; // [primitive_class_num] -> primitive_class_inf

std::vector<int> pin_layer_offset; // [0..num_pins-1]
std::vector<int> pin_width_offset; // [0..num_pins-1]
std::vector<int> pin_height_offset; // [0..num_pins-1]
std::vector<int> pin_class; // [0..num_pins-1]
Expand Down Expand Up @@ -1531,6 +1536,14 @@ enum e_Fc_type {
* relation to the switches from the architecture file, *
* not the expanded list of switches that is built *
* at the end of build_rr_graph *
* *
* @param arch_opin_between_dice_switch: Index of the switch type that *
* connects output pins (OPINs) *to* this segment from *
* *another die (layer)*. Note that this index is in *
* relation to the switches from the architecture file, *
* not the expanded list of switches that is built at *
* the end of build_rr_graph *
* *
* frac_cb: The fraction of logic blocks along its length to which this *
* segment can connect. (i.e. internal population). *
* frac_sb: The fraction of the length + 1 switch blocks along the segment *
Expand All @@ -1554,6 +1567,7 @@ struct t_segment_inf {
int length;
short arch_wire_switch;
short arch_opin_switch;
short arch_opin_between_dice_switch = -1;
float frac_cb;
float frac_sb;
bool longline;
Expand All @@ -1568,7 +1582,7 @@ struct t_segment_inf {
};

inline bool operator==(const t_segment_inf& a, const t_segment_inf& b) {
return a.name == b.name && a.frequency == b.frequency && a.length == b.length && a.arch_wire_switch == b.arch_wire_switch && a.arch_opin_switch == b.arch_opin_switch && a.frac_cb == b.frac_cb && a.frac_sb == b.frac_sb && a.longline == b.longline && a.Rmetal == b.Rmetal && a.Cmetal == b.Cmetal && a.directionality == b.directionality && a.parallel_axis == b.parallel_axis && a.cb == b.cb && a.sb == b.sb;
return a.name == b.name && a.frequency == b.frequency && a.length == b.length && a.arch_wire_switch == b.arch_wire_switch && a.arch_opin_switch == b.arch_opin_switch && a.arch_opin_between_dice_switch == b.arch_opin_between_dice_switch && a.frac_cb == b.frac_cb && a.frac_sb == b.frac_sb && a.longline == b.longline && a.Rmetal == b.Rmetal && a.Cmetal == b.Cmetal && a.directionality == b.directionality && a.parallel_axis == b.parallel_axis && a.cb == b.cb && a.sb == b.sb;
}

/*provide hashing for t_segment_inf to enable the use of many std containers.
Expand Down Expand Up @@ -1957,6 +1971,9 @@ struct t_arch {
t_power_arch* power = nullptr;
t_clock_arch* clocks = nullptr;

//determine which layers in multi-die FPGAs require to build global routing resources
std::vector<bool> layer_global_routing;

// Constants
// VCC and GND cells are special virtual cells that are
// used to handle the constant network of the device.
Expand Down Expand Up @@ -1984,9 +2001,10 @@ struct t_arch {
std::unordered_map<std::string, std::vector<t_lut_element>> lut_elements;

//The name of the switch used for the input connection block (i.e. to
//connect routing tracks to block pins).
//This should correspond to a switch in Switches
std::string ipin_cblock_switch_name;
//connect routing tracks to block pins). tracks can be connected to
// ipins through the same die or from other dice, each of these
//types of connections requires a different switch, all names should correspond to a switch in Switches.
std::vector<std::string> ipin_cblock_switch_name;

std::vector<t_grid_def> grid_layouts; //Set of potential device layouts

Expand Down
18 changes: 18 additions & 0 deletions libs/libarchfpga/src/physical_types_util.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -670,6 +670,24 @@ bool is_opin(int ipin, t_physical_tile_type_ptr type) {
return false;
}

bool is_pin_conencted_to_layer(t_physical_tile_type_ptr type, int ipin, int from_layer, int to_layer, int num_of_avail_layer) {
if (type->is_empty()) { //if type is empty, there is no pins
return false;
}
//ipin should be a valid pin in physical type
VTR_ASSERT(ipin < type->num_pins);
int pin_layer = from_layer + type->pin_layer_offset[ipin];
//if pin_offset specifies a layer that doesn't exist in arch file, we do a wrap around
pin_layer = (pin_layer < num_of_avail_layer) ? pin_layer : pin_layer % num_of_avail_layer;
if (from_layer == to_layer || pin_layer == to_layer) {
return true;
} else {
return false;
}
//not reachable
return false;
}

// TODO: Remove is_input_type / is_output_type / is_io_type as part of
// https://github.com/verilog-to-routing/vtr-verilog-to-routing/issues/1193
bool is_input_type(t_physical_tile_type_ptr type) {
Expand Down
3 changes: 3 additions & 0 deletions libs/libarchfpga/src/physical_types_util.h
Original file line number Diff line number Diff line change
Expand Up @@ -117,6 +117,9 @@
///@brief Returns true if the absolute physical pin index is an output of the given physical tile type
bool is_opin(int ipin, t_physical_tile_type_ptr type);

///@brief Returns true if the specified pin is located at "from_layer" and it is connected to "to_layer"
bool is_pin_conencted_to_layer(t_physical_tile_type_ptr type, int ipin, int from_layer, int to_layer);

///@brief Returns true if the given physical tile type can implement a .input block type
bool is_input_type(t_physical_tile_type_ptr type);
///@brief Returns true if the given physical tile type can implement a .output block type
Expand Down
2 changes: 1 addition & 1 deletion libs/libarchfpga/src/read_fpga_interchange_arch.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -2337,7 +2337,7 @@ struct ArchReader {
arch_->Chans.chan_y_dist.width = 0;
arch_->Chans.chan_y_dist.xpeak = 0;
arch_->Chans.chan_y_dist.dc = 0;
arch_->ipin_cblock_switch_name = std::string("generic");
arch_->ipin_cblock_switch_name.push_back(std::string("generic"));
arch_->SBType = WILTON;
arch_->Fs = 3;
default_fc_.specified = true;
Expand Down
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