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Route 3d #2330
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Route 3d #2330
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732081b
add an extra tag for layer offset in pinlocation tag and modified pro…
saaramahmoudi cf993ad
added a pin_layer_offset to t_physical_tile_type data structure
saaramahmoudi 58a121e
debug: VTR_ASSERT was flipped for layer_offset
saaramahmoudi f671707
ProcessPinLocations function updated to work with layer_offset requir…
saaramahmoudi e28de59
minor debugging, initialize the pin assignment with layer_offset
saaramahmoudi aaf7ec2
LoadPinLoc updated to work with layer offset derived from pin_loc->as…
saaramahmoudi 5e24125
parsing architecture file using pinlocations layer_offset
saaramahmoudi 09f9675
added layer_offset to 3d architecture file to confirm parsing archite…
saaramahmoudi e5d5545
Merge branch 'place_3d' of https://github.com/verilog-to-routing/vtr-…
saaramahmoudi dec2998
completed LoadPinLoc function with layer_offset
saaramahmoudi 29880da
Merge branch 'place_3d' of https://github.com/verilog-to-routing/vtr-…
saaramahmoudi 3a26065
Merge branch 'master' of https://github.com/verilog-to-routing/vtr-ve…
saaramahmoudi 261e9dc
Merge branch 'place_3d' of https://github.com/verilog-to-routing/vtr-…
saaramahmoudi 0766883
Merge branch 'master' of https://github.com/verilog-to-routing/vtr-ve…
saaramahmoudi 7bd4605
modified the pin to track connection to account for layer_number to s…
saaramahmoudi ee5e622
modified alloc_and_load_track_to_pin_lookup to account for layer_num
saaramahmoudi 914f436
fixed track to pin map dumping in the echo file
saaramahmoudi a131f45
changed the build_rr_* functions to pass the correct layer to rr_node…
saaramahmoudi c202ee1
fix all compiler issues and runtime problem, rr graph is incomplete i…
saaramahmoudi 4023854
Merge branch 'place_3d' of https://github.com/verilog-to-routing/vtr-…
saaramahmoudi 118fa1f
updated get_undir_opin_connections
saaramahmoudi 3fc1354
tracks can find IPINS on the other layers to connect to them
saaramahmoudi 01fd70c
Merge branch 'place_3d' of https://github.com/verilog-to-routing/vtr-…
saaramahmoudi b2ecf09
updated pin_to_track and track_to_pin data structure to work with 3D …
saaramahmoudi aa791c5
removed hardcoding layer numbers and add type_layer to account for ea…
saaramahmoudi e4728e4
updated alloc_and_load_pin_to_track_map to calculate type_layer and l…
saaramahmoudi fdd0cea
changed alloc_and_load_track_to_pin_lookup arguments to account for p…
saaramahmoudi 7b4e136
make format
saaramahmoudi 5ed3948
Merge branch 'place_3d' of https://github.com/verilog-to-routing/vtr-…
saaramahmoudi 207d2e0
filled physical_type_layer in device_grid.cpp and moved it to device_…
saaramahmoudi 0fcb403
Merge branch 'master' into inter_die_communication
saaramahmoudi 8339cba
Merge branch 'place_3d' of https://github.com/verilog-to-routing/vtr-…
saaramahmoudi 050e4ca
fixed some hardcoding of layer_offset
saaramahmoudi 9bbda8d
Merge branch 'inter_die_communication' of https://github.com/verilog-…
saaramahmoudi d077d2f
make format
saaramahmoudi 9bc75f4
fixed the seg fault causing by hardcoding the layer_num
saaramahmoudi dbb9932
Merge branch 'master' into inter_die_communication
saaramahmoudi 6449dea
added a new tag for architecture file to specify which FPGA die requi…
saaramahmoudi 9682ab8
Merge branch 'place_3d' of https://github.com/verilog-to-routing/vtr-…
saaramahmoudi 9f4b401
avoid building extra routing resources on base die when there is only…
saaramahmoudi 3a45917
minor bug in parsing the arch file for global resource routing
saaramahmoudi e796be1
make format
saaramahmoudi 9a45936
fixed lookahead warning for dice without global routing resources
saaramahmoudi de1125f
added a child tag for track to ipin switch, updated corresponding dat…
saaramahmoudi 0844bda
changed switch id for multi-die connections
saaramahmoudi 90bc0e2
added edge delay for opin to track connection
saaramahmoudi 7941fa3
added a simple arch for test multi-die FPGAs
saaramahmoudi 7e8ca99
make format
saaramahmoudi aa037ba
opins/ipins in each layer can be connected to tracks within the same …
saaramahmoudi d8704a9
opins in layer 0 for 2-dice FPGA fabric can be connected to both laye…
saaramahmoudi 54f065e
make format
saaramahmoudi 302917c
debug: in 2d cases had some edge duplication since pin_layer and laye…
saaramahmoudi 7b3d1c0
simplify arch file to wrap around layer_offset in case of being invalid
saaramahmoudi f4a9c71
resolved conflicts with master branch after removing route tree
saaramahmoudi e70a168
make format
saaramahmoudi 59cbee5
debug: fixed memory corruption in rr_graph
saaramahmoudi b76fa10
debug: layer_offset set correctly if subtile has more than 1 capacity
saaramahmoudi 7082ac3
Merge branch 'master' into inter_die_communication
saaramahmoudi c464514
Merge branch 'master' into inter_die_communication
saaramahmoudi 00bc1cb
added a helper function to determine whether pin is connected to anot…
saaramahmoudi 7908c2d
added S4 multi-die arch file
saaramahmoudi 07c46bb
Merge branch 'master' into inter_die_communication
saaramahmoudi fa998a4
removed physical_type_layer from device_ctx and add a helper function…
saaramahmoudi 6ba16ce
updated architecture 3d_k4_N4_90nm.xml to connect only OPINS to diffe…
saaramahmoudi cc62834
applied PR suggestion from VB
saaramahmoudi e992891
make format
saaramahmoudi 0935ca2
3d S4 arch with only OPINS connected
saaramahmoudi 4e1f1a2
Merge branch 'master' into inter_die_communication
saaramahmoudi c07ce4f
Merge branch 'master' into inter_die_communication
saaramahmoudi b5067ab
koios architecture with OPINS/IPINS connected to other layers
saaramahmoudi 63bc65a
add arch file for koios when only OPINS are connected to other layers
saaramahmoudi 3512591
factor out wrap around in rr_graph
saaramahmoudi 08e5d56
fix lookahead_map to work with inter_prog for each layer
saaramahmoudi 2955943
add support for inter dice switch while reading rr graph
saaramahmoudi 8a28f6e
debug: rr graph was generated incorrectly with only OPINs connected t…
saaramahmoudi ef52ac1
make format
saaramahmoudi f3bc909
fixed compiler warning related to null pointer dereference
saaramahmoudi fd2ef48
Merge branch 'master' into inter_die_communication
saaramahmoudi ec82c03
debug: pin to track map matrix size updated
saaramahmoudi 146021e
Merge branch 'inter_die_communication' of https://github.com/verilog-…
saaramahmoudi b264d40
resolved conflits with flat router test
saaramahmoudi 72e4b39
Architecture added for 3d Graphic
saaramahmoudi 2330613
print switch type info in arch.echo
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Don't forget these to do's: should do them now or file an issue to remember them.