Merge pull request #2330 from verilog-to-routing/inter_die_communication

Route 3d

Author: vaughnbetz

libs/libarchfpga/src/echo_arch.cpp

@@ -231,7 +231,11 @@ void PrintArchInfo(FILE* Echo, const t_arch* arch) {
             break;
     }
 
-    fprintf(Echo, "\tInput Connect Block Switch Name: %s\n", arch->ipin_cblock_switch_name.c_str());
+    fprintf(Echo, "\tInput Connect Block Switch Name Within a Same Die: %s\n", arch->ipin_cblock_switch_name[0].c_str());
+    //if there is more than one layer available, print the connection block switch name that is used for connection between two dice
+    if (arch->grid_layouts.size() > 1) {
+        fprintf(Echo, "\tInput Connect Block Switch Name Between Two Dice: %s\n", arch->ipin_cblock_switch_name[1].c_str());
+    }
 
     fprintf(Echo, "*************************************************\n\n");
     //Switch list
@@ -280,8 +284,13 @@ void PrintArchInfo(FILE* Echo, const t_arch* arch) {
 
         if (seg.directionality == UNI_DIRECTIONAL) {
             //wire_switch == arch_opin_switch
-            fprintf(Echo, "\t\t\t\ttype unidir mux_name %s\n",
+            fprintf(Echo, "\t\t\t\ttype unidir mux_name for within die connections: %s\n",
                     arch->Switches[seg.arch_wire_switch].name.c_str());
+            //if there is more than one layer available, print the segment switch name that is used for connection between two dice
+            if (arch->grid_layouts.size() > 1) {
+                fprintf(Echo, "\t\t\t\ttype unidir mux_name for between two dice connections: %s\n",
+                        arch->Switches[seg.arch_opin_between_dice_switch].name.c_str());
+            }
         } else { //Should be bidir
             fprintf(Echo, "\t\t\t\ttype bidir wire_switch %s arch_opin_switch %s\n",
                     arch->Switches[seg.arch_wire_switch].name.c_str(),

libs/libarchfpga/src/physical_types.h

@@ -575,6 +575,9 @@ constexpr int DEFAULT_SWITCH = -2;
  * pinloc: Is set to true if a given pin exists on a certain position of a
  *         block. Derived from pin_location_distribution/pin_loc_assignments
  *
+ * pin_layer_offset/pin_width_offset/pin_height_offset: offset from the anchor point
+ * of the block type in the x,y, and layer (dice number) direction.
+ *
  * pin_location_distribution: The pin distribution type
  * num_pin_loc_assignments: The number of strings within each pin_loc_assignments
  * pin_loc_assignments: The strings for a custom pin location distribution.
@@ -609,17 +612,18 @@ constexpr int DEFAULT_SWITCH = -2;
  * logical_tile_index: index of the corresponding logical block type
  *
  * In general, the physical tile is a placeable physical resource on the FPGA device,
- * and it is allowed to contain an heterogeneous set of logical blocks (pb_types).
+ * and it is allowed to contain a heterogeneous set of logical blocks (pb_types).
  *
  * Each physical tile must specify at least one sub tile, that is a physical location
  * on the sub tiles stacks. This means that a physical tile occupies an (x, y) location on the grid,
  * and it has at least one sub tile slot that allows for a placement within the (x, y) location.
  *
  * Therefore, to identify the location of a logical block within the device grid, we need to
- * specify three different coordinates:
+ * specify four different coordinates:
  *      - x         : horizontal coordinate
  *      - y         : vertical coordinate
  *      - sub tile  : location within the sub tile stack at an (x, y) physical location
+ *      -layer_num  : the layer that block is located at. In case of a single die, layer_num is 0.
  *
  * A physical tile is heterogeneous as it allows the placement of different kinds of logical blocks within,
  * that can share the same (x, y) placement location.
@@ -650,6 +654,7 @@ struct t_physical_tile_type {
     int primitive_class_starting_idx = -1;
     std::unordered_map<int, t_class> primitive_class_inf; // [primitive_class_num] -> primitive_class_inf
 
+    std::vector<int> pin_layer_offset;                // [0..num_pins-1]
     std::vector<int> pin_width_offset;                // [0..num_pins-1]
     std::vector<int> pin_height_offset;               // [0..num_pins-1]
     std::vector<int> pin_class;                       // [0..num_pins-1]
@@ -1531,6 +1536,14 @@ enum e_Fc_type {
  *                   relation to the switches from the architecture file,    *
  *                   not the expanded list of switches that is built         *
  *                   at the end of build_rr_graph                            *
+ *                                                                           *
+ * @param arch_opin_between_dice_switch: Index of the switch type that       *
+ *                   connects output pins (OPINs) *to* this segment from     *
+ *                   *another die (layer)*. Note that this index is in       *
+ *                   relation to the switches from the architecture file,    *
+ *                   not the expanded list of switches that is built at      *
+ *                   the end of build_rr_graph                               *
+ *                                                                           *
  * frac_cb:  The fraction of logic blocks along its length to which this     *
  *           segment can connect.  (i.e. internal population).               *
  * frac_sb:  The fraction of the length + 1 switch blocks along the segment  *
@@ -1554,6 +1567,7 @@ struct t_segment_inf {
     int length;
     short arch_wire_switch;
     short arch_opin_switch;
+    short arch_opin_between_dice_switch = -1;
     float frac_cb;
     float frac_sb;
     bool longline;
@@ -1568,7 +1582,7 @@ struct t_segment_inf {
 };
 
 inline bool operator==(const t_segment_inf& a, const t_segment_inf& b) {
-    return a.name == b.name && a.frequency == b.frequency && a.length == b.length && a.arch_wire_switch == b.arch_wire_switch && a.arch_opin_switch == b.arch_opin_switch && a.frac_cb == b.frac_cb && a.frac_sb == b.frac_sb && a.longline == b.longline && a.Rmetal == b.Rmetal && a.Cmetal == b.Cmetal && a.directionality == b.directionality && a.parallel_axis == b.parallel_axis && a.cb == b.cb && a.sb == b.sb;
+    return a.name == b.name && a.frequency == b.frequency && a.length == b.length && a.arch_wire_switch == b.arch_wire_switch && a.arch_opin_switch == b.arch_opin_switch && a.arch_opin_between_dice_switch == b.arch_opin_between_dice_switch && a.frac_cb == b.frac_cb && a.frac_sb == b.frac_sb && a.longline == b.longline && a.Rmetal == b.Rmetal && a.Cmetal == b.Cmetal && a.directionality == b.directionality && a.parallel_axis == b.parallel_axis && a.cb == b.cb && a.sb == b.sb;
 }
 
 /*provide hashing for t_segment_inf to enable the use of many std containers.
@@ -1963,6 +1977,9 @@ struct t_arch {
     t_power_arch* power = nullptr;
     t_clock_arch* clocks = nullptr;
 
+    //determine which layers in multi-die FPGAs require to build global routing resources
+    std::vector<bool> layer_global_routing;
+
     // Constants
     // VCC and GND cells are special virtual cells that are
     // used to handle the constant network of the device.
@@ -1990,9 +2007,10 @@ struct t_arch {
     std::unordered_map<std::string, std::vector<t_lut_element>> lut_elements;
 
     //The name of the switch used for the input connection block (i.e. to
-    //connect routing tracks to block pins).
-    //This should correspond to a switch in Switches
-    std::string ipin_cblock_switch_name;
+    //connect routing tracks to block pins). tracks can be connected to
+    // ipins through the same die or from other dice, each of these
+    //types of connections requires a different switch, all names should correspond to a switch in Switches.
+    std::vector<std::string> ipin_cblock_switch_name;
 
     std::vector<t_grid_def> grid_layouts; //Set of potential device layouts
 

libs/libarchfpga/src/physical_types_util.cpp

@@ -670,6 +670,24 @@ bool is_opin(int ipin, t_physical_tile_type_ptr type) {
         return false;
 }
 
+bool is_pin_conencted_to_layer(t_physical_tile_type_ptr type, int ipin, int from_layer, int to_layer, int num_of_avail_layer) {
+    if (type->is_empty()) { //if type is empty, there is no pins
+        return false;
+    }
+    //ipin should be a valid pin in physical type
+    VTR_ASSERT(ipin < type->num_pins);
+    int pin_layer = from_layer + type->pin_layer_offset[ipin];
+    //if pin_offset specifies a layer that doesn't exist in arch file, we do a wrap around
+    pin_layer = (pin_layer < num_of_avail_layer) ? pin_layer : pin_layer % num_of_avail_layer;
+    if (from_layer == to_layer || pin_layer == to_layer) {
+        return true;
+    } else {
+        return false;
+    }
+    //not reachable
+    return false;
+}
+
 // TODO: Remove is_input_type / is_output_type / is_io_type as part of
 // https://github.com/verilog-to-routing/vtr-verilog-to-routing/issues/1193
 bool is_input_type(t_physical_tile_type_ptr type) {

libs/libarchfpga/src/physical_types_util.h

@@ -117,6 +117,9 @@
 ///@brief Returns true if the absolute physical pin index is an output of the given physical tile type
 bool is_opin(int ipin, t_physical_tile_type_ptr type);
 
+///@brief Returns true if the specified pin is located at "from_layer" and it is connected to "to_layer"
+bool is_pin_conencted_to_layer(t_physical_tile_type_ptr type, int ipin, int from_layer, int to_layer, int num_of_avail_layer);
+
 ///@brief Returns true if the given physical tile type can implement a .input block type
 bool is_input_type(t_physical_tile_type_ptr type);
 ///@brief Returns true if the given physical tile type can implement a .output block type

libs/libarchfpga/src/read_fpga_interchange_arch.cpp

@@ -2337,7 +2337,7 @@ struct ArchReader {
         arch_->Chans.chan_y_dist.width = 0;
         arch_->Chans.chan_y_dist.xpeak = 0;
         arch_->Chans.chan_y_dist.dc = 0;
-        arch_->ipin_cblock_switch_name = std::string("generic");
+        arch_->ipin_cblock_switch_name.push_back(std::string("generic"));
         arch_->SBType = WILTON;
         arch_->Fs = 3;
         default_fc_.specified = true;