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Node naming, including hierarchical history in Yosys+Odin-II #2086

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Merged
merged 4 commits into from
Jul 15, 2022

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@sdamghan sdamghan commented Jul 6, 2022

Signed-off-by: Seyed Alireza Damghani [email protected]

Description

As Yosys generates a coarse-grained BLIF file for Odin-II partial mapper, all BLIF components were interpreted as black boxes at the beginning of Odin-II partial mapping. Therefore, node names were generated based on the type of each subcircuit, which was a unique name and did not include hierarchical information about modules/submodules. This PR extracts the hierarchical information related to each node from the name of its output signals and then sets the node(and its nets) name(s) based on the operation type of each node and the hierarchical information.

P.S: the similar approach is taken in Odin-II, which makes the readability of netlists better and eases the tracking of the critical path in the final VTR timing analysis.

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Motivation and Context

How Has This Been Tested?

Types of changes

  • Bug fix (change which fixes an issue)
  • New feature (change which adds functionality)
  • Breaking change (fix or feature that would cause existing functionality to change)

Checklist:

  • My change requires a change to the documentation
  • I have updated the documentation accordingly
  • I have added tests to cover my changes
  • All new and existing tests passed

@sdamghan sdamghan added the Yosys+Odin-II The Yosys+Odin-II synthesizer: the Yosys coarse-grained Tcl script and Odin-II partial mapping flow label Jul 6, 2022
@sdamghan sdamghan force-pushed the yosys_odin_net_names branch from 282ed2b to b0c5de9 Compare July 6, 2022 21:57
@github-actions github-actions bot added the Odin Odin II Logic Synthesis Tool: Unsorted item label Jul 6, 2022
@sdamghan sdamghan force-pushed the yosys_odin_net_names branch 5 times, most recently from 59b0404 to f0442e8 Compare July 8, 2022 18:22
@sdamghan sdamghan force-pushed the yosys_odin_net_names branch 2 times, most recently from 7a133be to 191330a Compare July 14, 2022 18:56
…ut pin name,

		 (should be unique for each subcircuit) to enhance the readability
		 and ease of CP tracking in VTR final timing analysis

Signed-off-by: Seyed Alireza Damghani <[email protected]>
@sdamghan sdamghan force-pushed the yosys_odin_net_names branch from d943a46 to 3defc89 Compare July 15, 2022 11:42
sdamghan added 3 commits July 15, 2022 09:15
…hical naming style

	 instead of node-type-encoded naming, when extracting names from Yosys
	 coarse-grained BLIF file

Signed-off-by: Seyed Alireza Damghani <[email protected]>
…ic/hdl_include** config files

Signed-off-by: Seyed Alireza Damghani <[email protected]>
@sdamghan sdamghan force-pushed the yosys_odin_net_names branch from 3defc89 to 549e334 Compare July 15, 2022 12:16
@sdamghan sdamghan merged commit 0f23dde into verilog-to-routing:master Jul 15, 2022
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