[Doc]: fix minor typos in the libs/EXTERNAL/CMakeList and vtr_reg_basic/hdl_include** config files

Signed-off-by: Seyed Alireza Damghani <[email protected]>

Author: sdamghan

libs/EXTERNAL/CMakeLists.txt

@@ -20,7 +20,7 @@ if(${ODIN_USE_YOSYS} OR ${WITH_YOSYS})
     add_subdirectory(libyosys)
 
     # In addition to libyosys in the build folder, we copy the libyosys directory
-    # into a temporary folder in the VTR root, name Yosys, to have access to Yosys 
+    # into a temporary folder in the VTR root, named Yosys, to have access to Yosys 
     # execs for using in VTR scripts (similar to VPR/vpr or ODIN_II/odin_II)
     add_custom_target(vtr-yosys ALL 
                       DEPENDS yosys

vtr_flow/tasks/regression_tests/vtr_reg_basic/hdl_include_odin/config/config.txt

@@ -2,13 +2,14 @@
 # Configuration file for running experiments                    #
 #                                                               #
 # This config file is testing the ability to specify include    #
-# files that should pass to the VTR frontend with the top       #
-# module of the benchmark (ch_intrinsic_top.v). This is done    #
-# by specifying two Verilog header files that provide essential # 
-# definitions, and memory_controller design that provides the   #
-# design of an internal component for ch_intrinsic_top. If the  #
-# include files are not properly included during compilation    #
-# the benchmark is incomplete and the flow will error out.      #
+# files that should be passed to the VTR Odin-II frontend with  #
+# the top module of the benchmark (ch_intrinsic_modified.v).    #
+# This is done by specifying two Verilog header files that      #
+# provide essential definitions, and memory_controller design   #
+# that provides the design of an internal component for         #
+# "ch_intrinsic_modified.v". If the include files are not       #
+# properly included during compilation the benchmark is         #
+# incomplete and the flow will error out.                       #
 #################################################################
 
 # Path to directory of circuits to use

vtr_flow/tasks/regression_tests/vtr_reg_basic/hdl_include_yosys/config/config.txt

@@ -2,13 +2,14 @@
 # Configuration file for running experiments                    #
 #                                                               #
 # This config file is testing the ability to specify include    #
-# files that should pass to the VTR frontend with the top       #
-# module of the benchmark (ch_intrinsic_top.v). This is done    #
-# by specifying two Verilog header files that provide essential # 
-# definitions, and memory_controller design that provides the   #
-# design of an internal component for ch_intrinsic_top. If the  #
-# include files are not properly included during compilation    #
-# the benchmark is incomplete and the flow will error out.      #
+# files that should be passed to the VTR Yosys frontend with    #
+# the top module of the benchmark (ch_intrinsic_modified.v).    #
+# This is done by specifying two Verilog header files that      #
+# provide essential definitions, and memory_controller design   #
+# that provides the design of an internal component for         #
+# "ch_intrinsic_modified.v". If the include files are not       #
+# properly included during compilation the benchmark is         #
+# incomplete and the flow will error out.                       #
 #################################################################
 
 # Path to directory of circuits to use

vtr_flow/tasks/regression_tests/vtr_reg_basic/hdl_include_yosys_odin/config/config.txt

@@ -2,13 +2,14 @@
 # Configuration file for running experiments                    #
 #                                                               #
 # This config file is testing the ability to specify include    #
-# files that should pass to the VTR frontend with the top       #
-# module of the benchmark (ch_intrinsic_top.v). This is done    #
-# by specifying two Verilog header files that provide essential # 
-# definitions, and memory_controller design that provides the   #
-# design of an internal component for ch_intrinsic_top. If the  #
-# include files are not properly included during compilation    #
-# the benchmark is incomplete and the flow will error out.      #
+# files that should be passed to the VTR Yosys+Odin-II frontend #
+# with the top module of the benchmark (ch_intrinsic_modified). #
+# This is done by specifying two Verilog header files that      #
+# provide essential definitions, and memory_controller design   #
+# that provides the design of an internal component for         #
+# "ch_intrinsic_modified.v". If the include files are not       #
+# properly included during compilation the benchmark is         #
+# incomplete and the flow will error out.                       #
 #################################################################
 
 # Path to directory of circuits to use