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verilog-to-routing / vtr-verilog-to-routing Public

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Node naming, including hierarchical history in Yosys+Odin-II #2086

Merged

sdamghan merged 4 commits intoverilog-to-routing:masterverilog-to-routing/vtr-verilog-to-routing:masterfrom

sdamghan:yosys_odin_net_namessdamghan/vtr-verilog-to-routing:yosys_odin_net_namesCopy head branch name to clipboard

Jul 15, 2022

Conversation Commits4 (4)Checks Files changed

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Commits on Jul 15, 2022

[Yosys+Odin-II]: replace Yosys RTLIL subcircuit names with their output pin name,
sdamghan
committed
[Infra]: add "decode_names" to Yosys+Odin-II's options to use hierarchical naming style
sdamghan
committed
[Doc]: add the decode names option to the Yosys+Odin-II docs
sdamghan
committed
[Doc]: fix minor typos in the libs/EXTERNAL/CMakeList and vtr_reg_basic/hdl_include** config files
sdamghan
committed

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