[Arch] Added Zero ASIC's Z1000 eFPGA Architecture #3158
Merged
Conversation
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
github-actions
bot
added
infra
|
More details about the architecture can be found here: https://github.com/siliconcompiler/logiklib/tree/main/logiklib/zeroasic/z1000
|
|
The bug in the packer is described in issue #2729 Once that is resolved, much more circuits can be run on this architecture. The target external pin utilization of {0.8, 0.6} is far too strict for this architecture and causes it to be unable to pack more than around 50/60% of the device. The packer should relax the target pin utilization if it fails to pack, but it is currently not doing that correctly. |
Zero ASIC uses VPR as part of its open-source FPGA CAD flow (Logik). Because of this, its architecture XML file is also open-source. This brings in Zero ASIC's Z1000 architecture. A 2048 4-LUT/FF architecture with 1024 GPIOs and can support up to 4 unique clock domains. I had to slightly modify the architecture file since the Z1000 uses custom register primitives which its synthesis front-end can target instead of regular ".latch" primitives. To get around this, I added a custom mode to the BLE to use the ".latch" primitive instead of the register primitives. Since the pins for the ".latch" primitive and the register primitives have one-to-one correspondance, this should have no affect on VPR's execution. In order for these circuits to route properly, the z1000 RR graph must also be provided. Included these as zip files and added a make command which will extract the RR graphs. Zipped, this file is around 2 MB, unzipped it is 90 MB. Added a tasks to NightlyTest7 which runs the MCNC benchmarks that could fit on this device. There is currently an issue in the packer causing it to give up too early and not pack as much as it can; the circuits affected by this bug have been commented out and will be uncommented once that bug is fixed.
AlexandreSinger
force-pushed
the
feature-arch-z1000
branch
from
a6042ac to
be3960f
Compare
vaughnbetz
approved these changes
Jun 21, 2025
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
Zero ASIC uses VPR as part of its open-source FPGA CAD flow (Logik). Because of this, its architecture XML file is also open-source.
This brings in Zero ASIC's Z1000 architecture. A 2048 4-LUT/FF architecture with 1024 GPIOs and can support up to 4 unique clock domains.
I had to slightly modify the architecture file since the Z1000 uses custom register primitives which its synthesis front-end can target instead of regular ".latch" primitives. To get around this, I added a custom mode to the BLE to use the ".latch" primitive instead of the register primitives. Since the pins for the ".latch" primitive and the register primitives have one-to-one correspondance, this should have no affect on VPR's execution.
In order for these circuits to route properly, the z1000 RR graph must also be provided. Included these as zip files and added a make command which will extract the RR graphs. Zipped, this file is around 2 MB, unzipped it is 90 MB.
Added a tasks to NightlyTest7 which runs the MCNC benchmarks that could fit on this device. There is currently an issue in the packer causing it to give up too early and not pack as much as it can; the circuits affected by this bug have been commented out and will be uncommented once that bug is fixed.