Skip to content

Commit 8164e63

Browse files
AlexandreSingerAlexandreSinger
authored
Merge pull request #3158 from verilog-to-routing/feature-arch-z1000
[Arch] Added Zero ASIC's Z1000 eFPGA Architecture
2 parents 39e5c88 + be3960f commit 8164e63

File tree

15 files changed

+31802
-1
lines changed

15 files changed

+31802
-1
lines changed

‎.github/workflows/nightly_test_manual.yml

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -50,6 +50,7 @@ jobs:
5050
make get_ispd_benchmarks
5151
./dev/upgrade_vtr_archs.sh
5252
make get_symbiflow_benchmarks
53+
make get_zeroasic_rr_graphs
5354
5455
# Build VTR using the default build options.
5556
- name: 'Build VTR'
@@ -133,4 +134,4 @@ jobs:
133134
with:
134135
name: nightly_tests_golden
135136
path: |
136-
vtr_flow/**/vtr_reg_nightly*/**/golden_results.txt
137+
vtr_flow/**/vtr_reg_nightly*/**/golden_results.txt

‎CMakeLists.txt

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -360,6 +360,14 @@ add_custom_target(get_symbiflow_benchmarks
360360
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
361361
COMMENT "Downloading (~100MB) and extracting SymbiFlow architectures (~2.7GB) into VTR source tree.")
362362

363+
#
364+
# Zero ASIC RR Graph Files
365+
#
366+
add_custom_target(get_zeroasic_rr_graphs
367+
COMMAND ./vtr_flow/scripts/get_zeroasic_rr_graphs.py --vtr_flow_dir ./vtr_flow
368+
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
369+
COMMENT "Downloading (~2MB) and extracting Zero ASIC RR graphs (~0.1GB) into VTR source tree.")
370+
363371
#
364372
# Unit Testing
365373
#

‎vtr_flow/arch/zeroasic/README.md

Lines changed: 17 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,17 @@
1+
# Zero ASIC Architectures
2+
3+
These are the VTR captures of the Zero ASIC architectures.
4+
5+
The orginal Zero ASIC architectures can be found in logiklib here:
6+
https://github.com/siliconcompiler/logiklib
7+
8+
These architectures have been slightly modified to work with VTR's CAD flow
9+
(i.e. synthesis) and VTR's benchmark suites.
10+
11+
The RR graphs of these architectures are required in order to route circuits
12+
on them. These RR graphs can be very large, so they are stored in zip format.
13+
To unzip them, run the following command in the root VTR directory:
14+
15+
```sh
16+
make get_zeroasic_rr_graphs
17+
```

‎vtr_flow/arch/zeroasic/z1000/.gitignore

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1 @@
1+
z1000_rr_graph.xml

‎vtr_flow/arch/zeroasic/z1000/z1000.xml

Lines changed: 31611 additions & 0 deletions
Large diffs are not rendered by default.

‎vtr_flow/arch/zeroasic/z1000/z1000_rr_graph.zip

3.1 MB
Binary file not shown.

‎vtr_flow/scripts/get_zeroasic_rr_graphs.py

Lines changed: 67 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,67 @@
1+
#!/usr/bin/env python3
2+
"""
3+
Script to get the Zero ASIC RR graphs.
4+
"""
5+
6+
import sys
7+
import os
8+
import argparse
9+
import subprocess
10+
import textwrap
11+
12+
13+
def parse_args():
14+
"""
15+
Parses and returns script's arguments
16+
"""
17+
18+
description = textwrap.dedent(
19+
"""
20+
Extracts the RR graphs for the Zero ASIC architectures which are
21+
stored in zip format to reduce the amount of space they take up.
22+
"""
23+
)
24+
parser = argparse.ArgumentParser(
25+
formatter_class=argparse.ArgumentDefaultsHelpFormatter, description=description
26+
)
27+
28+
parser.add_argument(
29+
"--vtr_flow_dir",
30+
required=True,
31+
help="The 'vtr_flow' directory under the VTR tree.",
32+
)
33+
34+
return parser.parse_args()
35+
36+
37+
def main():
38+
"""
39+
Main function
40+
"""
41+
42+
args = parse_args()
43+
44+
# A list of the zipped RR graphs to uncompress.
45+
zipped_rr_graphs = [
46+
f"{args.vtr_flow_dir}/arch/zeroasic/z1000/z1000_rr_graph.zip",
47+
]
48+
49+
# For each zipped RR graph, unzip it into its directory.
50+
for zipped_rr_graph in zipped_rr_graphs:
51+
# Check that the file exists.
52+
if not os.path.exists(zipped_rr_graph):
53+
print(f"Error: Unable to find zipped RR graph: {zipped_rr_graph}")
54+
sys.exit(1)
55+
56+
# Unzip it.
57+
print(f"Unzipping RR graph: {zipped_rr_graph}")
58+
subprocess.call(
59+
f"unzip {zipped_rr_graph} -d {os.path.dirname(zipped_rr_graph)}",
60+
shell=True,
61+
)
62+
63+
sys.exit(0)
64+
65+
66+
if __name__ == "__main__":
67+
main()

‎vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/task_list.txt

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -9,3 +9,4 @@ regression_tests/vtr_reg_nightly_test7/3d_cb_titan_other_auto_bb
99
regression_tests/vtr_reg_nightly_test7/3d_cb_titan_other_cube_bb
1010
regression_tests/vtr_reg_nightly_test7/3d_sb_titan_other_auto_bb
1111
regression_tests/vtr_reg_nightly_test7/3d_sb_titan_other_per_layer_bb
12+
regression_tests/vtr_reg_nightly_test7/z1000_qor

‎vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/z1000_qor/config/config.txt

Lines changed: 55 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,55 @@
1+
##############################################
2+
# Configuration file for running experiments
3+
##############################################
4+
5+
# NOTE: To run this task, the Z1000 RR graph is needed. This file needs to be
6+
# decompressed in order to run. In the root VTR directory, run:
7+
# make get_zeroasic_rr_graphs
8+
9+
# Path to directory of circuits to use
10+
circuits_dir=benchmarks/blif/4
11+
12+
# Path to directory of architectures to use
13+
archs_dir=arch/zeroasic/z1000
14+
15+
# Add architectures to list to sweep
16+
arch_list_add=z1000.xml
17+
additional_files_list_add=--read_rr_graph,z1000_rr_graph.xml
18+
19+
# Add circuits to list to sweep
20+
# These are the MCNC circuits which could theoretically fit on the Z1000 architecture.
21+
# The Z1000 architecture has 1024 4-LUTs, 1024 registers, and 1024 GPIOs
22+
# It can support up to 4 clock domains.
23+
# NOTE: Some of these circuit have been disabled due to the packer not packing
24+
# densely enough and is giving up too early.
25+
# circuit_list_add=alu4.blif
26+
# circuit_list_add=apex2.blif
27+
circuit_list_add=apex4.blif
28+
# circuit_list_add=bigkey.blif
29+
# circuit_list_add=des.blif
30+
# circuit_list_add=diffeq.blif
31+
# circuit_list_add=dsip.blif
32+
circuit_list_add=ex5p.blif
33+
circuit_list_add=misex3.blif
34+
# circuit_list_add=s298.blif
35+
# circuit_list_add=seq.blif
36+
circuit_list_add=tseng.blif
37+
38+
# Constrain the clocks
39+
# circuit_constraint_list_add=(bigkey.blif, constraints=../../../../constraints/bigkey_clk_constraints.xml)
40+
# circuit_constraint_list_add=(diffeq.blif, constraints=../../../../constraints/diffeq_clk_constraints.xml)
41+
# circuit_constraint_list_add=(dsip.blif, constraints=../../../../constraints/dsip_clk_constraints.xml)
42+
# circuit_constraint_list_add=(s298.blif, constraints=../../../../constraints/s298_clk_constraints.xml)
43+
circuit_constraint_list_add=(tseng.blif, constraints=../../../../constraints/tseng_clk_constraints.xml)
44+
45+
# Parse info and how to parse
46+
parse_file=vpr_fixed_chan_width.txt
47+
48+
# How to parse QoR info
49+
qor_parse_file=qor_fixed_chan_width.txt
50+
51+
# Pass requirements
52+
pass_requirements_file=pass_requirements_fixed_chan_width.txt
53+
54+
# Pass the script params while writing the vpr constraints.
55+
script_params=-starting_stage vpr -track_memory_usage --route_chan_width 100 --device z1000 --clock_modeling route --constant_net_method route --const_gen_inference none --sweep_dangling_primary_ios off --sweep_dangling_primary_ios off --sweep_dangling_nets off -allow_dangling_combinational_nodes on --sweep_constant_primary_outputs off --sweep_dangling_blocks off

‎vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/z1000_qor/config/golden_results.txt

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,5 @@
1+
arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time
2+
z1000.xml apex4.blif common 29.71 vpr 203.62 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 9 -1 -1 success v8.0.0-13106-g6d09dd1bc release IPO VTR_ASSERT_LEVEL=1 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-06-21T14:37:57 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/z1000_qor 208512 9 19 1271 1290 0 1101 271 20 20 400 -1 z1000 54.8 MiB 0.47 16997.6 11026 58087 17321 40200 566 203.6 MiB 0.56 0.01 14.0975 5.13665 -80.5734 -5.13665 nan 0.00 0.00186463 0.0016551 0.136222 0.11788 -1 -1 -1 -1 21788 19.7893 21788 19.7893 8071 34480 24954100 15595479 0 0 1.07648e+06 2691.20 20 83760 329916 -1 20.1611 nan -329.835 -20.1611 0 0 -1 -1 -1 203.6 MiB 4.85 0.230065 0.20045 203.6 MiB -1 22.94
3+
z1000.xml ex5p.blif common 27.85 vpr 202.37 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 8 -1 -1 success v8.0.0-13106-g6d09dd1bc release IPO VTR_ASSERT_LEVEL=1 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-06-21T14:37:57 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/z1000_qor 207228 8 63 1072 1135 0 922 268 20 20 400 -1 z1000 53.2 MiB 0.44 15638.6 9720 59815 19602 39922 291 202.4 MiB 0.53 0.01 16.9602 5.31138 -224.813 -5.31138 nan 0.00 0.00171384 0.00146613 0.127829 0.11045 -1 -1 -1 -1 17656 19.1497 17656 19.1497 6581 26611 15881306 9924577 0 0 1.07648e+06 2691.20 17 83760 329916 -1 20.6364 nan -861.644 -20.6364 0 0 -1 -1 -1 202.4 MiB 3.09 0.202018 0.177108 202.4 MiB -1 22.91
4+
z1000.xml misex3.blif common 29.42 vpr 203.29 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 14 -1 -1 success v8.0.0-13106-g6d09dd1bc release IPO VTR_ASSERT_LEVEL=1 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-06-21T14:37:57 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/z1000_qor 208168 14 14 1411 1425 0 1187 277 20 20 400 -1 z1000 55.2 MiB 0.55 17282.1 11327 54397 15164 38394 839 203.3 MiB 0.53 0.01 17.6523 5.26756 -65.1328 -5.26756 nan 0.00 0.00218546 0.00193189 0.141025 0.121572 -1 -1 -1 -1 22004 18.5375 22004 18.5375 7704 34644 21739132 14189209 0 0 1.07648e+06 2691.20 18 83760 329916 -1 20.3277 nan -244.181 -20.3277 0 0 -1 -1 -1 203.3 MiB 4.37 0.235825 0.206077 203.3 MiB -1 23.06
5+
z1000.xml tseng.blif common 25.72 vpr 203.57 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 52 -1 -1 success v8.0.0-13106-g6d09dd1bc release IPO VTR_ASSERT_LEVEL=1 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-06-21T14:37:57 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/z1000_qor 208460 52 122 1483 1605 1 802 337 20 20 400 -1 z1000 55.0 MiB 0.85 12144.9 5560 67141 18977 47877 287 203.6 MiB 0.40 0.01 3.40282e+35 3.40282e+35 -4.15144e+37 -3.40282e+35 3.40282e+35 0.00 0.00194566 0.00174471 0.121328 0.10932 -1 -1 -1 -1 9673 12.0611 9673 12.0611 2803 11729 3503391 2076039 0 0 1.07648e+06 2691.20 11 83760 329916 -1 21.8428 21.8428 -3701.87 -21.8428 0 0 -1 -1 -1 203.6 MiB 0.73 0.188029 0.170083 203.6 MiB -1 22.86

‎vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/z1000_qor/constraints/bigkey_clk_constraints.xml

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,7 @@
1+
<vpr_constraints tool_name="vpr">
2+
<partition_list>
3+
<partition name="pclk"><add_atom name_pattern="pclk" />
4+
<add_region subtile="-1" x_high="1" x_low="1" y_high="1" y_low="1" />
5+
</partition>
6+
</partition_list>
7+
</vpr_constraints>

‎vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/z1000_qor/constraints/diffeq_clk_constraints.xml

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,7 @@
1+
<vpr_constraints tool_name="vpr">
2+
<partition_list>
3+
<partition name="pclk"><add_atom name_pattern="pclk" />
4+
<add_region subtile="-1" x_high="1" x_low="1" y_high="1" y_low="1" />
5+
</partition>
6+
</partition_list>
7+
</vpr_constraints>

‎vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/z1000_qor/constraints/dsip_clk_constraints.xml

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,7 @@
1+
<vpr_constraints tool_name="vpr">
2+
<partition_list>
3+
<partition name="pclk"><add_atom name_pattern="pclk" />
4+
<add_region subtile="-1" x_high="1" x_low="1" y_high="1" y_low="1" />
5+
</partition>
6+
</partition_list>
7+
</vpr_constraints>

‎vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/z1000_qor/constraints/s298_clk_constraints.xml

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,7 @@
1+
<vpr_constraints tool_name="vpr">
2+
<partition_list>
3+
<partition name="clock"><add_atom name_pattern="clock" />
4+
<add_region subtile="-1" x_high="1" x_low="1" y_high="1" y_low="1" />
5+
</partition>
6+
</partition_list>
7+
</vpr_constraints>

‎vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/z1000_qor/constraints/tseng_clk_constraints.xml

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,7 @@
1+
<vpr_constraints tool_name="vpr">
2+
<partition_list>
3+
<partition name="pclk"><add_atom name_pattern="pclk" />
4+
<add_region subtile="-1" x_high="1" x_low="1" y_high="1" y_low="1" />
5+
</partition>
6+
</partition_list>
7+
</vpr_constraints>

0 commit comments

Comments
 (0)