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[OpenFPGA] Update #2970

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amin1377
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Update OpenFPGA branch with the master branch

vaughnbetz and others added 30 commits February 8, 2025 17:22
…-24.3.0

Bump black from 20.8b1 to 24.3.0
Improved the documentation on how chains are handled in the prepacker.
The prepacker segments chains into multiple molecules (where each
molecule can fit into a single cluster). The prepacker maintains
MoleculeChainIds to the chain these molecules are a part of. This allows
the cluster legalizer to easily put the molecules into clusters and
understand when a molecule is part of a special chain (for gain
calculation).
…eanup

[Prepack] Improved Documentation on Molecule Chains
APPack is a Full Legalizer which modifies the Packer and Placer to try
and improve their solutions based on a given Flat Placement. Integrated
this into the AP Flow by converting the Partial Placement generated by
the Global Placer into a Flat Placement and calling the Packer and
Placer.

Kept the original, Naive Full Legalizer as something to compare to and
since it may be useful to keep this legalizer around.

Added tests for both the Naive and APPack Full Legalizers, leaving the
other tests to always run on the default AP Flow.
…galizer

[AP] Added APPack to the AP Flow as a Full Legalizer
After each pack, the partition regions are checked to see if any of the
partition regions are overfilled. During this process, the overfilled
partition regions were stored in the Floorplanning context (likely for
legacy reasons). This was then read from a few lines later in another
function.

Turned this into a local variable instead of a global variable.
[Pack] Removed Global Overfilled Partition Regions
falling into random macro placement while we have available
subtiles in the selected location.
Improve nightly test manual and regenerate QoR results
The PlaceMacros only require the Clustering and atom/arch info to be
constructed; after which they are never modified. Since they are
unchanged by the placement, they were out of place in the
BlkLocRegistry.

Moved them to the clustering context since they only make sense once the
clusters are loaded.

This will make it easier to separate out the initial placement from the
SA placer.
Vaughn thought that the place macros made more sense in the placement
context instead of the clustering context.
Found some arguments to the Cluster Legalizer Constructor which
ultimately led to no change. Removed them to make the Cluster Legalizer
easier to work with.
Change NightlyTest workflow to not run automatically
[Place] Moved PlaceMacros Out of BlkLocRegistry
instead of going to random placement, going to neighbour placement if no available subtile found
minor optimization on available subtile vector and other style updates
updated QoR for vtr_reg_strong(_odin) based on above placement behaviour
multiclock_mcnc and updated golden results.
amin1377 and others added 10 commits April 7, 2025 13:06
[Place] rename get_initial_move_lim to get_place_inner_loop_num_move
…-run

[vtr_flow] Changed Triggers for Second Run
…format

Set InsertNewlineAtEOF in .clang-format file
Timing was intermixed into the packer. It appears as though the code
originally was designed to recalculate the timing information every so
often in the packer, but the idea was abandoned. This left timing code
in disperse locations around the Packer and the timing was being
recomputed every time clustering was restarted which was unecessary.

Collecting all of the timing information from the Packer into a single
object called PreClusterTimingManager which abstracts all of the timing
info in the Packer.

The ultimate goal is to bring this Manager class into the AP flow to be
used together with the Global Placer. By sharing this manager class, the
AP flow may be able to update the timing info with flat placement
information to make the timing more accurate.
…ager

[Pack][Timing] Abstracted How Timing is Used in the Packer
@amin1377 amin1377 requested a review from tangxifan April 10, 2025 23:05
@github-actions github-actions bot added VPR VPR FPGA Placement & Routing Tool Odin Odin II Logic Synthesis Tool: Unsorted item libarchfpga Library for handling FPGA Architecture descriptions docs Documentation lang-cpp C/C++ code infra Project Infrastructure build Build system scripts Utility & Infrastructure scripts lang-python Python code lang-make CMake/Make code lang-hdl Hardware Description Language (Verilog/VHDL) lang-shell Shell scripts (bash etc.) libvtrutil external_libs liblog Parmys labels Apr 10, 2025
@tangxifan
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@amin1377 can you avoid rebase and use merge instead? The commit history is now complicated. Thanks!

@amin1377 amin1377 closed this Apr 11, 2025
@amin1377 amin1377 deleted the openfpga_update branch April 11, 2025 17:41
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build Build system docs Documentation external_libs infra Project Infrastructure lang-cpp C/C++ code lang-hdl Hardware Description Language (Verilog/VHDL) lang-make CMake/Make code lang-python Python code lang-shell Shell scripts (bash etc.) libarchfpga Library for handling FPGA Architecture descriptions liblog libvtrutil Odin Odin II Logic Synthesis Tool: Unsorted item Parmys scripts Utility & Infrastructure scripts VPR VPR FPGA Placement & Routing Tool
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