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Pass actual fc instead of fc_max to connect to pins #2661

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Merged
merged 21 commits into from
Oct 8, 2024

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saaramahmoudi
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Description

This PR addresses the issue mentioned in Issue #2641.

Motivation and Context

How Has This Been Tested?

I tested the branch with my examples with fc_override with different pins. @WhiteNinjaZ has also tested the branch on a couple more benchmarks and confirmed that it works properly.

Types of changes

  • Bug fix (change which fixes an issue)
  • New feature (change which adds functionality)
  • Breaking change (fix or feature that would cause existing functionality to change)

QoR:

We expect the RR graph to change based on this change. Thus, I have initiated Titan and VTR benchmarks to compare QoR with the master branch. Will attach the results as soon as it is ready.

@saaramahmoudi saaramahmoudi requested a review from vaughnbetz July 23, 2024 20:14
@github-actions github-actions bot added VPR VPR FPGA Placement & Routing Tool lang-cpp C/C++ code labels Jul 23, 2024
@saaramahmoudi saaramahmoudi changed the title Pass actual fc instead of fmax to connect to pins Pass actual fc instead of fc_max to connect to pins Jul 23, 2024
@saaramahmoudi
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@vaughnbetz

These links are the results for this branch for VTR and Titan benchmarks:

@vaughnbetz
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A few QoR failures; they seem to be higher routing areas, maybe expected due to the Fc handling change. I checked vtr_reg_basic and it is routing area increases (37%, above the 30% tolerance) but only on the diffeq circuit (which is small). That seems likely to be OK and just needing a golden result update; other failures are hopefully similar.

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Looks good; I just suggest some Doxygen comments for the modified routines (which didn't have them before, but adding them would make you a force for good @saaramahmoudi !).

@vaughnbetz
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QoR looks good; roughly a tie for VTR and actually a bit better for Titan.
Can you also compare the routing area per tile on Titan (can just do one circuit) to confirm it is very close before and after the change? That will confirm we're getting the same number of switches when you don't change the architecture.

@saaramahmoudi
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QoR looks good; roughly a tie for VTR and actually a bit better for Titan. Can you also compare the routing area per tile on Titan (can just do one circuit) to confirm it is very close before and after the change? That will confirm we're getting the same number of switches when you don't change the architecture.

The spreadsheet I attached for Titan has the area per tile for all circuits (parse_results_master.txt and parse_results.txt tabs). Geomean averaged over all circuits; the routing area per tile for the master branch is "18519," and for my branch, it is "18518", which confirms that we are getting a close number in both branches.

@vaughnbetz
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Thanks, that looks good.

@vaughnbetz
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If you're able to add the requested comments we can merge. If you can't add those in the near future we could merge too (although it would be nice to get them in while we're looking at the code).

@saaramahmoudi
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If you're able to add the requested comments we can merge. If you can't add those in the near future we could merge too (although it would be nice to get them in while we're looking at the code).

I am adding the comments right now. After I push to the branch with updated golden results, I will ping you.

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Some commenting improvements and variable name improvements suggested.

bool channel_widths_unchanged(const t_chan_width& current, const t_chan_width& proposed);

/**
* @brief This routine calculate pin connections to tracks for a specific type on the Fc value defined for each pin in the architecture file.
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What is the difference between this routine and the one below it? From their comments they both seem to do the same thing. One returns a 5D matrix of vectors, and the other a 6D matrix, but other than that they don't seem different. Could one be deleted (don't worry about it if that is too much work, but we could put a TODO in if that's the better long term path).

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The one that returns the 6D matrix is written as a helper function for the other one. Basically, we first calculate the number of connections should be made for each pin for the current tile and save a relative track indices. Then, we return the 6D matrix and post process it to calculate the absolute track number and keep a vector of connection per each pin. Note that basically they return the same thing (6D matrix of int and 5D matrix of integer vector) but the logic within each function are different.

@saaramahmoudi
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@vaughnbetz applied requested changes, ready to merge!

@vaughnbetz vaughnbetz merged commit edbe700 into master Oct 8, 2024
35 of 53 checks passed
@vaughnbetz vaughnbetz deleted the pass_actual_fc_to_connect_to_pins branch October 8, 2024 00:45
@AlexandreSinger
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@vaughnbetz This PR failed the strong tests. After merging, master is now failing the strong tests...

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@saaramahmoudi Do you think this is a problem? Or do you think the golden solutions just need to be regenerated?

@saaramahmoudi
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@AlexandreSinger @vaughnbetz I think we just need to generate the golden results for those.

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@saaramahmoudi Perfect! Thats good news. Would you be able to do that in a PR? If not I can raise a PR tomorrow if I find time.

@saaramahmoudi
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@AlexandreSinger will raise a PR tomorrow!

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3 participants