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Merged
merged 21 commits into from
Oct 8, 2024
Merged

Pass actual fc instead of fc_max to connect to pins #2661

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7951434
Merge branch 'master' of https://github.com/verilog-to-routing/vtr-ve…
saaramahmoudi Jun 26, 2024
97b1be6
Merge branch 'fc_log' of https://github.com/verilog-to-routing/vtr-ve…
saaramahmoudi Jun 27, 2024
ccdb004
pass actual Fc through connection blocks functions to use pin-specifi…
saaramahmoudi Jun 27, 2024
d500dd6
Merge branch 'master' of https://github.com/verilog-to-routing/vtr-ve…
saaramahmoudi Jul 5, 2024
ceae381
Merge branch 'master' of https://github.com/verilog-to-routing/vtr-ve…
saaramahmoudi Jul 16, 2024
b1788cb
update load_perturbed_connection_block_pattern
saaramahmoudi Jul 22, 2024
c749a59
Merge branch 'master' of https://github.com/verilog-to-routing/vtr-ve…
saaramahmoudi Jul 22, 2024
2c38e77
Merge branch 'master' of https://github.com/verilog-to-routing/vtr-ve…
saaramahmoudi Jul 23, 2024
e06b192
removed extra log print
saaramahmoudi Jul 23, 2024
38dd40f
Merge branch 'master' into pass_actual_fc_to_connect_to_pins
saaramahmoudi Jul 25, 2024
3ed789e
Merge branch 'master' into pass_actual_fc_to_connect_to_pins
saaramahmoudi Jul 25, 2024
b017a26
Merge branch 'master' into pass_actual_fc_to_connect_to_pins
saaramahmoudi Aug 26, 2024
674623e
document some functions in rr_graph.cpp
saaramahmoudi Aug 26, 2024
757bc61
Merge branch 'master' into pass_actual_fc_to_connect_to_pins
saaramahmoudi Aug 27, 2024
f011e4b
updated golden results
saaramahmoudi Aug 29, 2024
592c0ab
Merge branch 'master' into pass_actual_fc_to_connect_to_pins
saaramahmoudi Aug 29, 2024
85fd2d0
update odin strong test
saaramahmoudi Aug 29, 2024
9b23a7e
Merge branch 'pass_actual_fc_to_connect_to_pins' of https://github.co…
saaramahmoudi Aug 29, 2024
54b9a2b
resolved conflicts with master branch
saaramahmoudi Oct 7, 2024
962d757
Merge branch 'master' into pass_actual_fc_to_connect_to_pins
saaramahmoudi Oct 7, 2024
3ea63b6
code refactoring, applied VB comment suggestions
saaramahmoudi Oct 7, 2024
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61 changes: 37 additions & 24 deletions vpr/src/route/rr_graph.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -106,8 +106,10 @@ static vtr::NdMatrix<std::vector<int>, 5> alloc_and_load_pin_to_track_map(const
const int* sets_per_seg_type);

static vtr::NdMatrix<int, 6> alloc_and_load_pin_to_seg_type(const e_pin_type pin_type,
const vtr::Matrix<int>& Fc,
const int seg_type_tracks,
const int Fc,
const int seg_index,
const int max_Fc,
const t_physical_tile_type_ptr Type,
const std::set<int> type_layer,
const bool perturb_switch_pattern,
Expand Down Expand Up @@ -284,16 +286,18 @@ static void alloc_and_load_tile_rr_graph(RRGraphBuilder& rr_graph_builder,
static float pattern_fmod(float a, float b);
static void load_uniform_connection_block_pattern(vtr::NdMatrix<int, 6>& tracks_connected_to_pin,
const std::vector<t_pin_loc>& pin_locations,
const vtr::Matrix<int>& Fc,
const int seg_index,
const int x_chan_width,
const int y_chan_width,
const int Fc,
const enum e_directionality directionality);

static void load_perturbed_connection_block_pattern(vtr::NdMatrix<int, 6>& tracks_connected_to_pin,
const std::vector<t_pin_loc>& pin_locations,
const int x_chan_width,
const int y_chan_width,
const int Fc,
const vtr::Matrix<int>& Fc,
const int seg_index,
const enum e_directionality directionality);

static std::vector<bool> alloc_and_load_perturb_opins(const t_physical_tile_type_ptr type, const vtr::Matrix<int>& Fc_out, const int max_chan_width, const std::vector<t_segment_inf>& segment_inf);
Expand Down Expand Up @@ -1147,7 +1151,7 @@ static void build_rr_graph(const t_graph_type graph_type,
segment_inf[k].name.c_str(),
Fc_out[i][j][k],
Fc_in[i][j][k]);
#endif /* VERBOSE */
#endif
VTR_ASSERT_MSG(Fc_out[i][j][k] == 0 || Fc_in[i][j][k] == 0,
"Pins must be inputs or outputs (i.e. can not have both non-zero Fc_out and Fc_in)");
}
Expand Down Expand Up @@ -3262,17 +3266,18 @@ static vtr::NdMatrix<std::vector<int>, 5> alloc_and_load_pin_to_track_map(const
}

/* get pin connections to tracks of the current segment type */
auto pin_to_seg_type_map = alloc_and_load_pin_to_seg_type(pin_type, num_seg_type_tracks, max_Fc, Type, type_layer, perturb_switch_pattern[seg_inf[iseg].seg_index], directionality);
auto pin_to_seg_type_map = alloc_and_load_pin_to_seg_type(pin_type, Fc, num_seg_type_tracks, seg_inf[iseg].seg_index, max_Fc, Type, type_layer, perturb_switch_pattern[seg_inf[iseg].seg_index], directionality);

/* connections in pin_to_seg_type_map are within that seg type -- i.e. in the [0,num_seg_type_tracks-1] range.
* now load up 'result' array with these connections, but offset them so they are relative to the channel
* as a whole */
for (auto type_layer_index : type_layer) {
for (int ipin = 0; ipin < Type->num_pins; ipin++) {
int cur_Fc = Fc[ipin][seg_inf[iseg].seg_index];
for (int iwidth = 0; iwidth < Type->width; iwidth++) {
for (int iheight = 0; iheight < Type->height; iheight++) {
for (int iside = 0; iside < 4; iside++) {
for (int iconn = 0; iconn < max_Fc; iconn++) {
for (int iconn = 0; iconn < cur_Fc; iconn++) {
for (auto connected_layer : get_layers_pin_is_connected_to(Type, type_layer_index, ipin)) {
int relative_track_ind = pin_to_seg_type_map[ipin][iwidth][iheight][connected_layer][iside][iconn];
if (relative_track_ind != OPEN) {
Expand All @@ -3299,8 +3304,10 @@ static vtr::NdMatrix<std::vector<int>, 5> alloc_and_load_pin_to_track_map(const
}

static vtr::NdMatrix<int, 6> alloc_and_load_pin_to_seg_type(const e_pin_type pin_type,
const vtr::Matrix<int>& Fc,
const int num_seg_type_tracks,
const int Fc,
const int seg_index,
const int max_Fc,
const t_physical_tile_type_ptr Type,
const std::set<int> type_layer,
const bool perturb_switch_pattern,
Expand Down Expand Up @@ -3334,7 +3341,7 @@ static vtr::NdMatrix<int, 6> alloc_and_load_pin_to_seg_type(const e_pin_type pin
size_t(Type->height), //[0..height-1]
size_t(grid.get_num_layers()), //[0..layer-1]
NUM_SIDES, //[0..NUM_SIDES-1]
size_t(Fc) //[0..Fc-1]
size_t(max_Fc) //[0..Fc-1]
},
OPEN); //Unconnected

Expand Down Expand Up @@ -3474,11 +3481,11 @@ static vtr::NdMatrix<int, 6> alloc_and_load_pin_to_seg_type(const e_pin_type pin
if (perturb_switch_pattern) {
load_perturbed_connection_block_pattern(tracks_connected_to_pin,
pin_ordering,
num_seg_type_tracks, num_seg_type_tracks, Fc, directionality);
num_seg_type_tracks, num_seg_type_tracks, Fc, seg_index, directionality);
} else {
load_uniform_connection_block_pattern(tracks_connected_to_pin,
pin_ordering,
num_seg_type_tracks, num_seg_type_tracks, Fc, directionality);
pin_ordering, Fc, seg_index,
num_seg_type_tracks, num_seg_type_tracks, directionality);
}

#ifdef ENABLE_CHECK_ALL_TRACKS
Expand Down Expand Up @@ -3623,9 +3630,10 @@ static float pattern_fmod(float a, float b) {

static void load_uniform_connection_block_pattern(vtr::NdMatrix<int, 6>& tracks_connected_to_pin,
const std::vector<t_pin_loc>& pin_locations,
const vtr::Matrix<int>& Fc,
const int seg_index,
const int x_chan_width,
const int y_chan_width,
const int Fc,
enum e_directionality directionality) {
/* Loads the tracks_connected_to_pin array with an even distribution of *
* switches across the tracks for each pin. For example, each pin connects *
Expand Down Expand Up @@ -3703,7 +3711,7 @@ static void load_uniform_connection_block_pattern(vtr::NdMatrix<int, 6>& tracks_
group_size = 2;
}

VTR_ASSERT((x_chan_width % group_size == 0) && (y_chan_width % group_size == 0) && (Fc % group_size == 0));
VTR_ASSERT((x_chan_width % group_size == 0) && (y_chan_width % group_size == 0));

/* offset is used to move to a different point in the track space if it is detected that
* the tracks being assigned overlap recently assigned tracks, with the goal of increasing
Expand All @@ -3717,19 +3725,22 @@ static void load_uniform_connection_block_pattern(vtr::NdMatrix<int, 6>& tracks_
int width = pin_locations[i].width_offset;
int height = pin_locations[i].height_offset;
int layer = pin_locations[i].layer_offset;
int pin_fc = Fc[pin][seg_index];

VTR_ASSERT(pin_fc % group_size == 0);

/* Bi-directional treats each track separately, uni-directional works with pairs of tracks */
for (int j = 0; j < (Fc / group_size); ++j) {
for (int j = 0; j < (pin_fc / group_size); ++j) {
int max_chan_width = (((side == TOP) || (side == BOTTOM)) ? x_chan_width : y_chan_width);

// if the number of tracks we can assign is zero break from the loop
if (max_chan_width == 0) {
break;
}
float step_size = (float)max_chan_width / (float)(Fc * num_phys_pins);
float step_size = (float)max_chan_width / (float)(pin_fc * num_phys_pins);

VTR_ASSERT(Fc > 0);
float fc_step = (float)max_chan_width / (float)Fc;
VTR_ASSERT(pin_fc > 0);
float fc_step = (float)max_chan_width / (float)pin_fc;

/* We may go outside the track ID space, because of offset, so use modulo arithmetic below. */

Expand All @@ -3756,7 +3767,7 @@ static void load_uniform_connection_block_pattern(vtr::NdMatrix<int, 6>& tracks_
int num_unassigned_tracks = 0;
int num_total_tracks = 0;

for (int j2 = 0; j2 < (Fc / group_size); ++j2) {
for (int j2 = 0; j2 < (pin_fc / group_size); ++j2) {
ftrack = pattern_fmod((i + offset + offset_increment) * step_size, fc_step) + (j2 * fc_step);
itrack = ((int)ftrack) * group_size;

Expand Down Expand Up @@ -3831,7 +3842,8 @@ static void load_perturbed_connection_block_pattern(vtr::NdMatrix<int, 6>& track
const std::vector<t_pin_loc>& pin_locations,
const int x_chan_width,
const int y_chan_width,
const int Fc,
const vtr::Matrix<int>& Fc,
const int seg_index,
enum e_directionality directionality) {
/* Loads the tracks_connected_to_pin array with an unevenly distributed *
* set of switches across the channel. This is done for inputs when *
Expand All @@ -3846,10 +3858,6 @@ static void load_perturbed_connection_block_pattern(vtr::NdMatrix<int, 6>& track

VTR_ASSERT(directionality == BI_DIRECTIONAL);

int Fc_dense = (Fc / 2) + 1;
int Fc_sparse = Fc - Fc_dense; /* Works for even or odd Fc */
int Fc_half[2];

int num_phys_pins = pin_locations.size();

for (int i = 0; i < num_phys_pins; ++i) {
Expand All @@ -3859,8 +3867,13 @@ static void load_perturbed_connection_block_pattern(vtr::NdMatrix<int, 6>& track
int height = pin_locations[i].height_offset;
int layer = pin_locations[i].layer_offset;

int pin_Fc = Fc[pin][seg_index];
int Fc_dense = ( pin_Fc / 2) + 1;
int Fc_sparse = pin_Fc - Fc_dense;
int Fc_half[2];

int max_chan_width = (((side == TOP) || (side == BOTTOM)) ? x_chan_width : y_chan_width);
float step_size = (float)max_chan_width / (float)(Fc * num_phys_pins);
float step_size = (float)max_chan_width / (float)(pin_Fc * num_phys_pins);

float spacing_dense = (float)max_chan_width / (float)(2 * Fc_dense);
float spacing_sparse = (float)max_chan_width / (float)(2 * Fc_sparse);
Expand Down
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