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Flat router test #2324
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Flat router test #2324
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… to 300 - Add flat router depop under nightly test 3
…romUnorderedMap functions instead
…_tile_pin_primitive_pin_delay - change t_physical_type_ptr to int
…in after file is being read
Should also add a 7-series architecture on some circuit(s). |
A too long python line to fix: styr.blif failed critical path (and related timing) tests for Odin II strong on the push, but not the pull (odd!). Looks like it's OK to change, and if it doesn't recur it's OK to ignore anyway. |
sry, thought that button would show the diff before creating a commit |
@vaughnbetz : Regarding the edge_remapped_ vector that we talked about before, I just checked the code, and it is already stored in a separate vector, and it is not in any hot data structure. |
Ah, that's good. We should move it to the RRGraphBuilder class so its lifetime is more limited though; best to minimize the long-lived state. |
@vaughnbetz: CIs are green, except for the documentation build failure. I'm not sure why it's failing. |
Some conflicts need to be resolved. |
Conflicts, nag, nag |
Done...I am now waiting for the CI tests and also running the QoR tests(VTR and Titan) just to be sure. |
Some QoR failures, although the one I looked in vtr_nightly3 seems to be OK (all due to a channel width increase of 31% on a small bgm design): |
…rch_timing.blif jacobi_stratixiv_arch_timing.blif from flat router test due to run-time
@vaughnbetz : I guess there is something wrong with vtr_reg_nightly_test_2. I also looked at other CI test(1, 2, 3) and non of them can run this test in the allocated run-time (they don't fail, but it seems that the test gets aborted) |
@vaughnbetz I guess this PR is finally ready to land! |
In this PR, the following tests have been added:
vtr_reg_nightly_test_2: ~ 4.2 hours
vtr_reg_nightly_test_3: ~2.3 hours
vtr_reg_strong: Overall, took about 12 minutes