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Jul 11, 2023
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1f62001
add flat_router strong test
amin1377 Apr 25, 2023
ddbdabb
Create a titan_other test for flat_router
amin1377 Apr 25, 2023
6ee5b70
add titan_quick_qor_flat_router under nightly_test_2
amin1377 Apr 26, 2023
3f9a38f
add vtr_reg_qor_chain_large_flat_router
amin1377 Apr 26, 2023
25f7d5b
Add flat router tests to task_list - otherwise they woudln't be cheke…
amin1377 Apr 27, 2023
bd31027
fix a typo under task list of nightly test 2
amin1377 Apr 27, 2023
e95220b
add flat_router test under task list of nightly test 3
amin1377 Apr 27, 2023
5b640ac
Merge branch 'master' of https://github.com/verilog-to-routing/vtr-ve…
amin1377 Apr 28, 2023
3ab41ef
Merge branch 'master' of https://github.com/verilog-to-routing/vtr-ve…
amin1377 May 12, 2023
a2bdcee
Merge branch 'min_chan_router_iteration' of https://github.com/verilo…
amin1377 May 15, 2023
6b0c7c8
change max_router iterations of flat_router test under nightly_test_3…
amin1377 May 15, 2023
fcd9ba2
Merge branch 'min_chan_router_iteration' of https://github.com/verilo…
amin1377 May 22, 2023
a618e62
remove titan_quick_qor_flat_router - add titan_other_flat_router
amin1377 May 22, 2023
65d09fb
add verify rr graph for flat_router
amin1377 May 22, 2023
3c02374
set is_flat_ field to true if intra-cluster lookahead is read from a …
amin1377 May 22, 2023
35fa1c1
add support to verify router lookahead
amin1377 May 22, 2023
a291db3
remove the previous function in the file - implement fromVector and F…
amin1377 May 24, 2023
f9db2fd
remove the fields related to tile sink
amin1377 May 24, 2023
a953883
fix the writing functions based on the new changes - only write inter…
amin1377 May 24, 2023
45af5f1
add toUnorderedMap and toVector to intra_cluster_serdes.h
amin1377 May 24, 2023
5cf0c9a
fix the intra cluster lookahead reader functions - Compute the tile m…
amin1377 May 24, 2023
1991fcf
fix a typo
amin1377 May 24, 2023
13498f1
add == opearator to Cost_Entry
amin1377 May 24, 2023
609a4d6
Add an assertion to check the number of sinks for each pin
amin1377 May 24, 2023
3eb9337
make format
amin1377 May 24, 2023
ec4fa04
disable writing rr-graph if flat-routing is enalbled
amin1377 May 25, 2023
98a79a8
While reading RR Graph, don't raise an error if the name starts with …
amin1377 May 25, 2023
a7deb2e
t_rr_edge_infor: remove the default value of is_remapped
amin1377 May 26, 2023
11c6833
add is_rr_id to emplace_back_edge function of rr_graph_builder
amin1377 May 26, 2023
9deb2f6
add intra_tile field to t_rr_switch_inf
amin1377 May 26, 2023
2e6303f
while loading the sw name, determine whether the sw is intra-cluster …
amin1377 May 26, 2023
b08f84d
add remapped to rr_graph_storage:emplace_back_edge
amin1377 May 26, 2023
a0e8a67
pass false as edge_remapped parameter for the edges created for clock…
amin1377 May 27, 2023
5262f51
add edge_remapped parameter to add_edge function of clockrrgraphbuilder
amin1377 May 27, 2023
e0cab99
pass load graph to functions that create graph which indicate whether…
amin1377 May 27, 2023
2a74a54
make format
amin1377 May 27, 2023
3075f08
fix the comment about switch types written in rr graph xml/serialized…
amin1377 May 29, 2023
e1f7a7f
remove vtr_reg_qor_chain_large_flat_router - reduce the number of cir…
amin1377 May 29, 2023
14c5fe9
Merge branch 'master' of https://github.com/verilog-to-routing/vtr-ve…
amin1377 May 29, 2023
8528925
add vpr_verify_router_lookahead_flat_router
amin1377 May 29, 2023
8a514af
comment out vpr_verify_router_lookahead_flat_router
amin1377 May 31, 2023
e9292cd
update titan_other_flat_router golden results
amin1377 May 31, 2023
0cdf182
update vpr_verify_rr_graph_flat_router golden results
amin1377 May 31, 2023
1755af3
update vtr_reg_qor_chain_depop_flat_router golden results
amin1377 May 31, 2023
0b94e25
update strong_flat_router golden results
amin1377 May 31, 2023
7bb4e93
Merge branch 'master' into flat_router_test
vaughnbetz May 31, 2023
d0ffc90
add comments on remapped parameter to add edges to rr graph
amin1377 Jun 7, 2023
35afe94
add comments on flat-router parts of router_lookahead_map and rr_grap…
amin1377 Jun 7, 2023
30cf8fb
Add comments on verify router lookahead in run_vtr_flow.py and add mo…
amin1377 Jun 8, 2023
e3b7994
Merge branch 'master' into flat_router_test
vaughnbetz Jun 8, 2023
84c2bde
break the long line in run_vtr_flow.py - explain more on edge switch …
Jun 12, 2023
4cb9b98
Merge branch 'master' of https://github.com/verilog-to-routing/vtr-ve…
Jun 12, 2023
2912a35
Merge branch 'master' into flat_router_test
duck2 Jun 13, 2023
00f6b9d
Merge branch 'master' into flat_router_test
amin1377 Jun 22, 2023
2aceaf6
remove seen_edge vector since it doesn't have significant effect on t…
amin1377 Jun 26, 2023
65c3a8f
add some comments above edge_remapped_
amin1377 Jun 26, 2023
1fa24ac
solve the conflicts with main
amin1377 Jul 1, 2023
e906852
clear edge_remap once done with building rr graph
Jul 2, 2023
511e909
update the results for vtr_reg_strong flat router
Jul 2, 2023
c6e7a57
update depop-flat-router nightly test 3
Jul 2, 2023
9503eae
remove SURF_desc_stratixiv_arch_timing.blif stap_steering_stratixiv_a…
amin1377 Jul 3, 2023
171ab85
update titan_other_flat_router golden results
amin1377 Jul 7, 2023
d61831e
Merge branch 'master' into flat_router_test
amin1377 Jul 10, 2023
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6 changes: 4 additions & 2 deletions libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h
Original file line number Diff line number Diff line change
Expand Up @@ -460,11 +460,13 @@ class RrGraphSerializer final : public uxsd::RrGraphBase<RrGraphContextTypes> {
//
// If the switch name is not present in the architecture, generate an
// error.
// If the graph is written when flat-routing is enalbed, the types of the switches inside of the rr_graph are also
// added to the XML file. These types are not added the data structure that contain arch switch types. It's remained
// as a future work to remove the arch_switch_types and use all_sw info under device_ctx instead.
bool found_arch_name = false;
std::string string_name = std::string(name);
for (const auto& arch_sw_inf: arch_switch_inf_) {
if (string_name == arch_sw_inf.name) {
string_name = arch_sw_inf.name;
if (string_name == arch_sw_inf.name || string_name.compare(0, 15, "Internal Switch") == 0) {
found_arch_name = true;
break;
}
Expand Down
235 changes: 49 additions & 186 deletions libs/libvtrcapnproto/intra_cluster_serdes.h
Original file line number Diff line number Diff line change
Expand Up @@ -16,201 +16,64 @@
#include "vpr_types.h"
#include "router_lookahead_map_utils.h"


void ToIntraClusterLookahead(std::unordered_map<t_physical_tile_type_ptr, util::t_ipin_primitive_sink_delays>& inter_tile_pin_primitive_pin_delay,
std::unordered_map<t_physical_tile_type_ptr, std::unordered_map<int, util::Cost_Entry>>& tile_min_cost,
const std::vector<t_physical_tile_type>& physical_tile_types,
const VprIntraClusterLookahead::Reader& intra_cluster_lookahead_builder);

void FromIntraClusterLookahead(VprIntraClusterLookahead::Builder& intra_cluster_lookahead_builder,
const std::unordered_map<t_physical_tile_type_ptr, util::t_ipin_primitive_sink_delays>& inter_tile_pin_primitive_pin_delay,
const std::unordered_map<t_physical_tile_type_ptr, std::unordered_map<int, util::Cost_Entry>>& tile_min_cost,
const std::vector<t_physical_tile_type>& physical_tile_types);
// Generic function to convert from Matrix capnproto message to vtr::NdMatrix.
//
// Template arguments:
// N = Number of matrix dimensions, must be fixed.
// CapType = Source capnproto message type that is a single element the
// Matrix capnproto message.
// CType = Target C++ type that is a single element of vtr::NdMatrix.
//
// Arguments:
// m_out = Target vtr::NdMatrix.
// m_in = Source capnproto message reader.
// copy_fun = Function to convert from CapType to CType.
void ToIntraClusterLookahead(std::unordered_map<t_physical_tile_type_ptr, util::t_ipin_primitive_sink_delays>& inter_tile_pin_primitive_pin_delay,
std::unordered_map<t_physical_tile_type_ptr, std::unordered_map<int, util::Cost_Entry>>& tile_min_cost,
const std::vector<t_physical_tile_type>& physical_tile_types,
const VprIntraClusterLookahead::Reader& intra_cluster_lookahead_builder) {

inter_tile_pin_primitive_pin_delay.clear();
tile_min_cost.clear();

int num_tile_types = intra_cluster_lookahead_builder.getPhysicalTileNumPins().size();
VTR_ASSERT(num_tile_types == (int)physical_tile_types.size());

std::vector<int> tile_num_pins(num_tile_types);
std::vector<int> tile_num_sinks(num_tile_types);

for (int tile_idx = 0; tile_idx < num_tile_types; tile_idx++) {
tile_num_pins[tile_idx] = intra_cluster_lookahead_builder.getPhysicalTileNumPins()[tile_idx];
tile_num_sinks[tile_idx] = intra_cluster_lookahead_builder.getTileNumSinks()[tile_idx];
}

int num_seen_sinks = 0;
int num_seen_pins = 0;
for(int tile_type_idx = 0; tile_type_idx < num_tile_types; tile_type_idx++) {
int cur_tile_num_pins = tile_num_pins[tile_type_idx];
t_physical_tile_type_ptr physical_type_ptr = &physical_tile_types[tile_type_idx];
inter_tile_pin_primitive_pin_delay[physical_type_ptr] = util::t_ipin_primitive_sink_delays(cur_tile_num_pins);
for(int pin_num = 0; pin_num < cur_tile_num_pins; pin_num++) {
inter_tile_pin_primitive_pin_delay[physical_type_ptr][pin_num].clear();
int pin_num_sinks = intra_cluster_lookahead_builder.getPinNumSinks()[num_seen_pins];
num_seen_pins++;
for(int sink_idx = 0; sink_idx < pin_num_sinks; sink_idx++) {
int sink_pin_num = intra_cluster_lookahead_builder.getPinSinks()[num_seen_sinks];
auto cost = intra_cluster_lookahead_builder.getPinSinkCosts()[num_seen_sinks];
inter_tile_pin_primitive_pin_delay[physical_type_ptr][pin_num].insert(std::make_pair(sink_pin_num,
util::Cost_Entry(cost.getDelay(), cost.getCongestion())));
num_seen_sinks++;
}


}
}

num_seen_sinks = 0;
for(int tile_type_idx = 0; tile_type_idx < num_tile_types; tile_type_idx++) {
int cur_tile_num_sinks = tile_num_sinks[tile_type_idx];
t_physical_tile_type_ptr physical_type_ptr = &physical_tile_types[tile_type_idx];
tile_min_cost[physical_type_ptr] = std::unordered_map<int, util::Cost_Entry>();
for(int sink_idx = 0; sink_idx < cur_tile_num_sinks; sink_idx++) {
int sink_num = intra_cluster_lookahead_builder.getTileSinks()[num_seen_sinks];
auto cost = intra_cluster_lookahead_builder.getTileMinCosts()[num_seen_sinks];
tile_min_cost[physical_type_ptr].insert(std::make_pair(sink_num,
util::Cost_Entry(cost.getDelay(), cost.getCongestion())));
num_seen_sinks++;

}
template<typename CapElemType, typename ElemType>
void toVector(std::vector<ElemType>& vec_out,
const typename capnp::List<CapElemType>::Reader& m_in,
const std::function<void(std::vector<ElemType>&,
int,
const ElemType&)>& copy_fun) {
int size = m_in.size();
vec_out.resize(size);
for(int idx = 0; idx < size; idx++) {
copy_fun(vec_out, idx, m_in[idx]);
}


}

void FromIntraClusterLookahead(VprIntraClusterLookahead::Builder& intra_cluster_lookahead_builder,
const std::unordered_map<t_physical_tile_type_ptr, util::t_ipin_primitive_sink_delays>& inter_tile_pin_primitive_pin_delay,
const std::unordered_map<t_physical_tile_type_ptr, std::unordered_map<int, util::Cost_Entry>>& tile_min_cost,
const std::vector<t_physical_tile_type>& physical_tile_types) {

::capnp::List<int64_t>::Builder physical_tile_num_pin_arr_builder;
::capnp::List<int64_t>::Builder pin_num_sink_arr_builder;
::capnp::List<int64_t>::Builder pin_sink_arr_builder;
::capnp::List<VprMapCostEntry>::Builder pin_sink_cost_builder;
::capnp::List<int64_t>::Builder tile_num_sinks_builder;
::capnp::List<int64_t>::Builder tile_sinks_builder;
::capnp::List<VprMapCostEntry>::Builder tile_sink_min_cost_builder;

int num_tile_types = physical_tile_types.size();

physical_tile_num_pin_arr_builder = intra_cluster_lookahead_builder.initPhysicalTileNumPins(num_tile_types);

// Count the number of pins for each tile
{
int total_num_pin = 0;
for (const auto& tile_type : physical_tile_types) {
const auto tile_pin_primitive_delay = inter_tile_pin_primitive_pin_delay.find(&tile_type);
if (tile_pin_primitive_delay == inter_tile_pin_primitive_pin_delay.end()) {
physical_tile_num_pin_arr_builder.set(tile_type.index, 0);
continue;
}
int tile_num_pins = tile_pin_primitive_delay->second.size();
physical_tile_num_pin_arr_builder.set(tile_type.index, tile_num_pins);
total_num_pin += tile_num_pins;
}

pin_num_sink_arr_builder = intra_cluster_lookahead_builder.initPinNumSinks(total_num_pin);
}

// Count the number of sinks for each pin
{
int pin_num = 0;
int total_pin_num_sinks = 0;
for (const auto& tile_type : physical_tile_types) {
const auto tile_pin_primitive_delay = inter_tile_pin_primitive_pin_delay.find(&tile_type);
if (tile_pin_primitive_delay == inter_tile_pin_primitive_pin_delay.end()) {
continue;
}
for (const auto& pin : tile_pin_primitive_delay->second) {
int pin_num_sinks = pin.size();
pin_num_sink_arr_builder.set(pin_num, pin_num_sinks);
pin_num++;
total_pin_num_sinks += pin_num_sinks;
}
}

pin_sink_arr_builder = intra_cluster_lookahead_builder.initPinSinks(total_pin_num_sinks);
pin_sink_cost_builder = intra_cluster_lookahead_builder.initPinSinkCosts(total_pin_num_sinks);
}

// Iterate over sinks of each pin and store the cost of getting to the sink from the respective pin and the sink ptc number
{
int pin_flat_sink_idx = 0;
for (const auto& tile_type : physical_tile_types) {
const auto tile_pin_primitive_delay = inter_tile_pin_primitive_pin_delay.find(&tile_type);
if (tile_pin_primitive_delay == inter_tile_pin_primitive_pin_delay.end()) {
continue;
}
for (const auto& pin : tile_pin_primitive_delay->second) {
for (const auto& sink : pin) {
pin_sink_arr_builder.set(pin_flat_sink_idx, sink.first);
pin_sink_cost_builder[pin_flat_sink_idx].setDelay(sink.second.delay);
pin_sink_cost_builder[pin_flat_sink_idx].setCongestion(sink.second.congestion);
pin_flat_sink_idx++;
}
}
}
template<typename CapKeyType, typename CapValType, typename KeyType, typename CostType>
void toUnorderedMap(
std::unordered_map<KeyType, CostType>& map_in,
const int begin_flat_idx,
const int end_flat_idx,
const typename capnp::List<CapKeyType>::Reader& m_out_key,
const typename capnp::List<CapValType>::Reader& m_out_val,
const std::function<void(std::unordered_map<KeyType, CostType>&,
const KeyType&,
const typename CapValType::Reader&)>& copy_fun) {

for(int flat_idx = begin_flat_idx; flat_idx < end_flat_idx; flat_idx++) {
copy_fun(map_in, m_out_key[flat_idx], m_out_val[flat_idx]);
}
}

template<typename CapElemType, typename ElemType>
void fromVector(typename capnp::List<CapElemType>::Builder& m_out,
const std::vector<ElemType>& vec_in,
const std::function<void(typename capnp::List<CapElemType>::Builder&,
int,
const ElemType&)>& copy_fun) {

// Store the information related to tile_min cost

tile_num_sinks_builder = intra_cluster_lookahead_builder.initTileNumSinks(num_tile_types);

// Count the number of sinks for each tile
{
int tile_total_num_sinks = 0;
for (const auto& tile_type : physical_tile_types) {
const auto tile_min_cost_entry = tile_min_cost.find(&tile_type);
if (tile_min_cost_entry == tile_min_cost.end()) {
tile_num_sinks_builder.set(tile_type.index, 0);
continue;
}
int tile_num_sinks = (int)tile_min_cost_entry->second.size();
tile_num_sinks_builder.set(tile_type.index, tile_num_sinks);
tile_total_num_sinks += tile_num_sinks;
}

tile_sinks_builder = intra_cluster_lookahead_builder.initTileSinks(tile_total_num_sinks);
tile_sink_min_cost_builder = intra_cluster_lookahead_builder.initTileMinCosts(tile_total_num_sinks);
for(int idx = 0; idx < (int)vec_in.size(); idx++) {
copy_fun(m_out, idx, vec_in[idx]);
}
}

// Iterate over sinks of each tile and store the minimum cost to get to that sink and the sink ptc number
{
int pin_flat_sink_idx = 0;
for (const auto& tile_type : physical_tile_types) {
const auto tile_min_cost_entry = tile_min_cost.find(&tile_type);
if (tile_min_cost_entry == tile_min_cost.end()) {
continue;
}
for (const auto& sink : tile_min_cost_entry->second) {
tile_sinks_builder.set(pin_flat_sink_idx, sink.first);
tile_sink_min_cost_builder[pin_flat_sink_idx].setDelay(sink.second.delay);
tile_sink_min_cost_builder[pin_flat_sink_idx].setCongestion(sink.second.congestion);
pin_flat_sink_idx++;
}
template<typename CapKeyType, typename CapValType, typename KeyType, typename CostType>
void FromUnorderedMap(
typename capnp::List<CapKeyType>::Builder& m_out_key,
typename capnp::List<CapValType>::Builder& m_out_val,
const KeyType out_offset,
const std::unordered_map<KeyType, CostType>& map_in,
const std::function<void(typename capnp::List<CapKeyType>::Builder&,
typename capnp::List<CapValType>::Builder&,
int,
const KeyType&,
const CostType&)>& copy_fun) {

int flat_idx = out_offset;
for (const auto& entry : map_in) {
copy_fun(m_out_key, m_out_val, flat_idx, entry.first, entry.second);
flat_idx++;
}
}

}


Expand Down
3 changes: 0 additions & 3 deletions libs/libvtrcapnproto/map_lookahead.capnp
Original file line number Diff line number Diff line change
Expand Up @@ -15,7 +15,4 @@ struct VprIntraClusterLookahead {
pinNumSinks @1 :List(Int64);
pinSinks @2 :List(Int64);
pinSinkCosts @3 :List(VprMapCostEntry);
tileNumSinks @4 :List(Int64);
tileSinks @5 :List(Int64);
tileMinCosts @6 :List(VprMapCostEntry);
}
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