Speciy used hardblocks to print their model in the blif generation phase

[sdamghan]

Signed-off-by: Seyed Alireza Damghani [email protected]

Description

Follow up on PR #1953
Hardblocks, used by Yosys elaborator, are flaged to print their .model in the final BLIF file

Related Issue

Motivation and Context

How Has This Been Tested?

Types of changes

• Bug fix (change which fixes an issue)
• New feature (change which adds functionality)
• Breaking change (fix or feature that would cause existing functionality to change)

Checklist:

• My change requires a change to the documentation
• I have updated the documentation accordingly
• I have added tests to cover my changes
• All new and existing tests passed

[sdamghan]

@aman26kbm - this PR should fix our problem in PR #1953. Would you mind verifying it?

[aman26kbm]

@karanmathur Please verify this (remember to use run_vtr_flow or run_vtr_task)

[karanmathur]

@sdamghan I ran run_vtr_flow.py with -elaborator yosys and the architecture file as arch/COFFE_22nm/k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml

Tested with hard block module int_sop_4

File with DSP instantiation :
yes_dsp.txt
File without:
no_dsp.txt

The flow passed without any errors for both , however in the vpr.out of yes_dsp, in the resource usage there are no dsp blocks
Resource usage...
Netlist
64 blocks of type: io
Architecture
288 blocks of type: io
Netlist
64 blocks of type: clb
Architecture
65 blocks of type: clb
Netlist
0 blocks of type: dsp_top
Architecture
2 blocks of type: dsp_top
Netlist
0 blocks of type: memory
Architecture
4 blocks of type: memory

whereas on running no_dsp there are 3 blocks of dsp.
Resource usage...
Netlist
144 blocks of type: io
Architecture
384 blocks of type: io
Netlist
8 blocks of type: clb
Architecture
120 blocks of type: clb
Netlist
3 blocks of type: dsp_top
Architecture
3 blocks of type: dsp_top
Netlist
0 blocks of type: memory
Architecture
6 blocks of type: memory

In abc0.out for yes_dsp there are warnings, attaching the file below:
abc.txt
These are the warnings:
Warning: Constant-0 drivers added to 1 non-driven nets in network "top":
\int_sop_4~0
Warning: The design has 2 root-level modules. The first one (top) will be used.
Hierarchy reader converted 1 instances of blackboxes.

Warning: Constant-0 drivers added to 1 non-driven nets in network "top":
\int_sop_4~0
Warning: The design has 2 root-level modules. The first one (top) will be used.
Hierarchy writer reintroduced 1 instances of blackboxes.

There are also warnings in elaboration.yosys.log regarding resizing of cell port by one bit extra, ax is supposed to be 9 bits but it extends it to 10, same with clk, reset get extended to 2 bits.
119 Warning: Resizing cell port top.int_sop_4_inst_0_O0.chainout from 64 bits to 65 bits.
120 Warning: Resizing cell port top.int_sop_4_inst_0_O0.resulta from 64 bits to 65 bits.
121 Warning: Resizing cell port top.int_sop_4_inst_0_O0.dy from 9 bits to 10 bits.
122 Warning: Resizing cell port top.int_sop_4_inst_0_O0.dx from 9 bits to 10 bits.
123 Warning: Resizing cell port top.int_sop_4_inst_0_O0.cy from 9 bits to 10 bits.
124 Warning: Resizing cell port top.int_sop_4_inst_0_O0.cx from 9 bits to 10 bits.
125 Warning: Resizing cell port top.int_sop_4_inst_0_O0.by from 9 bits to 10 bits.
126 Warning: Resizing cell port top.int_sop_4_inst_0_O0.bx from 9 bits to 10 bits.
127 Warning: Resizing cell port top.int_sop_4_inst_0_O0.ay from 9 bits to 10 bits.
128 Warning: Resizing cell port top.int_sop_4_inst_0_O0.ax from 9 bits to 10 bits.
129 Warning: Resizing cell port top.int_sop_4_inst_0_O0.reset from 1 bits to 2 bits.
130 Warning: Resizing cell port top.int_sop_4_inst_0_O0.clk from 1 bits to 2 bits.

odin.out shows no. of <HARD_IP> node as 1.

In conclusion the flow passes without any errors however it seems the hard block has not been incorporated. The issue might be related to the warnings in the abc0.out and/or the elaboration log files.

[aman26kbm]

Hi @sdamghan , did you get a chance to look into this?

[sdamghan]

Hi @sdamghan , did you get a chance to look into this?

Hi Aman, I am still working on it. Will provide more info soon

[sdamghan]

@karanmathur can you please test this branch again with new changes, recent changes should solve the issue.

[karanmathur]

@sdamghan It works fine now, I have tested it with some small designs. Currently, a bigger one is running, will let you know if any issue arises.

[karanmathur]

@sdamghan the bigger designs have also passed

[karanmathur]

@sdamghan the bigger designs have also passed

[aman26kbm]

I think we can merge this PR, @sdamghan

[sdamghan]

Sounds good, will merge it into the master branch