module top (input logic [8:0] ax,input logic [8:0] ay,input logic [8:0] bx,input logic [8:0] by,input logic [8:0] cx,input logic [8:0] cy,input logic [8:0] dx,input logic [8:0] dy,input logic clk,input logic rstn, output logic [63:0] resulta);

logic signed [63:0] chainout_0_O0;
int_sop_4 int_sop_4_inst_0_O0(.clk(clk),.reset(rstn),.mode_sigs(11'd0),.ax(ax),.ay(ay),.bx(bx),.by(by),.cx(cx),.cy(cy),.dx(dx),.dy(dy),.chainin(64'd0),.resulta(resulta),.chainout(chainout_0_O0));

endmodule