1 /usr/bin/env time -v /home/data1/karan/vtr-sdamghan-dsp/vtr-verilog-to-routing/abc/abc -c echo ""; echo "Load Netlist"; echo "============"; read 0_yes_dsp.odin.blif; time; echo ""; echo "Circuit Info"; echo "=========="; print_stats; print_latch; time; echo ""; echo "LUT Costs"; echo "========="; print_lut; time; echo ""; echo "Logic Opt + Techmap"; echo "==================="; strash; ifraig -v; scorr -v; dc2 -v; dch -f; if -K 6 -v; mfs2 -v; print_stats; time; echo ""; echo "Output Netlist"; echo "=============="; write_hie 0_yes_dsp.odin.blif 0_yes_dsp.raw.abc.blif; time; 2 ABC command line: "echo ""; echo "Load Netlist"; echo "============"; read 0_yes_dsp.odin.blif; time; echo ""; echo "Circuit Info"; echo "=========="; print_stats; print_latch; time; echo ""; echo "LUT Costs"; echo "========="; print_lut; time; echo ""; echo "Logic Opt + Techmap"; echo "==================="; strash; ifraig -v; scorr -v; dc2 -v; dch -f; if -K 6 -v; mfs2 -v; print_stats; time; echo ""; echo "Output Netlist"; echo "=============="; write_hie 0_yes_dsp.odin.blif 0_yes_dsp.raw.abc.blif; time;". 3 4 5 Load Netlist 6 ============ 7 Warning: Constant-0 drivers added to 1 non-driven nets in network "top": 8 \int_sop_4~0 9 Warning: The design has 2 root-level modules. The first one (top) will be used. 10 Hierarchy reader converted 1 instances of blackboxes. 11 elapse: 0.00 seconds, total: 0.00 seconds 12 13 Circuit Info 14 ========== 15 ^[[1;37mtop :^[[0m i/o = 202/ 213 lat = 0 nd = 217 edge = 64 cube = 64 lev = 1 16 The network is combinational. 17 elapse: 0.00 seconds, total: 0.00 seconds 18 19 LUT Costs 20 ========= 21 # The area/delay of k-variable LUTs: 22 # k area delay 23 1 1.00 1.00 24 2 1.00 1.00 25 3 1.00 1.00 26 4 1.00 1.00 27 elapse: 0.00 seconds, total: 0.00 seconds 28 29 Logic Opt + Techmap 30 =================== 31 Warning: The network is combinational (run "fraig" or "fraig_sweep"). 32 Starting: top : pi = 202 po = 213 and = 0 lev = 0 33 Rewrite: top : pi = 202 po = 213 and = 0 lev = 0 34 Refactor: top : pi = 202 po = 213 and = 0 lev = 0 35 Balance: top : pi = 202 po = 213 and = 0 lev = 0 36 Rewrite: top : pi = 202 po = 213 and = 0 lev = 0 37 RewriteZ: top : pi = 202 po = 213 and = 0 lev = 0 38 RefactorZ: top : pi = 202 po = 213 and = 0 lev = 0 39 RewriteZ: top : pi = 202 po = 213 and = 0 lev = 0 40 K = 6. Memory (bytes): Truth = 0. Cut = 56. Obj = 136. Set = 600. CutMin = no 41 Node = 0. Ch = 0. Total mem = 0.06 MB. Peak cut mem = 0.00 MB. 42 P: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec 43 P: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec 44 P: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec 45 E: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec 46 F: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec 47 E: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec 48 A: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec 49 E: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec 50 A: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec 51 E: Del = 0.00. Ar = 0.0. Edge = 0. Cut = 0. T = 0.00 sec 52 Total time = 0.00 sec 53 Warning: The network has only constant nodes. 54 Performing MFS with 202 PIs, 213 POs, 213 nodes (213 flexible, 0 fixed, 0 empty). 55 Nodes = 213. Try = 0. Resub = 0. Div = 0 (ave = 0). SAT calls = 0. Timeouts = 0. MaxDivs = 0. 56 Attempts : Remove 0 out of 0 ( 0.00 %) Resub 0 out of 0 ( 0.00 %) 57 Reduction: Nodes 0 out of 0 ( 0.00 %) Edges 0 out of 0 ( 0.00 %) 58 Win = 0.00 sec ( 0.00 %) 59 Div = 0.00 sec ( 0.00 %) 60 Cnf = 0.00 sec ( 0.00 %) 61 Sat = 0.00 sec ( 0.00 %) 62 Oth = 0.00 sec (100.00 %) 63 ALL = 0.00 sec (100.00 %) 64 ^[[1;37mtop :^[[0m i/o = 202/ 213 lat = 0 nd = 213 edge = 0 cube = 0 lev = 0 65 elapse: 0.00 seconds, total: 0.01 seconds 66 67 Output Netlist 68 ============== 69 Warning: Constant-0 drivers added to 1 non-driven nets in network "top": 70 \int_sop_4~0 71 Warning: The design has 2 root-level modules. The first one (top) will be used. 72 Hierarchy writer reintroduced 1 instances of blackboxes. 73 elapse: 0.00 seconds, total: 0.01 seconds 74 Command being timed: "/home/data1/karan/vtr-sdamghan-dsp/vtr-verilog-to-routing/abc/abc -c echo ""; echo "Load Netlist"; echo "============"; read 0_yes_dsp.odin.blif; time; echo ""; echo "Circuit Info"; echo "=========="; print_stats; print_latch; time; echo ""; echo "LUT Costs"; echo "========="; print_lut; time; echo ""; echo "Logic Opt + Techmap"; echo "==================="; strash; ifraig -v; scorr -v; dc2 -v; dch -f; if -K 6 -v; mfs2 -v; print_stats; time; echo ""; echo "Output Netlist"; echo "=============="; write_hie 0_yes_dsp.odin.blif 0_yes_dsp.raw.abc.blif; time;" 75 User time (seconds): 0.04 76 System time (seconds): 0.01 77 Percent of CPU this job got: 98% 78 Elapsed (wall clock) time (h:mm:ss or m:ss): 0:00.06 79 Average shared text size (kbytes): 0 80 Average unshared data size (kbytes): 0 81 Average stack size (kbytes): 0 82 Average total size (kbytes): 0 83 Maximum resident set size (kbytes): 34288 84 Average resident set size (kbytes): 0 85 Major (requiring I/O) page faults: 0 86 Minor (reclaiming a frame) page faults: 7408 87 Voluntary context switches: 1 88 Involuntary context switches: 1 89 Swaps: 0 90 File system inputs: 0 91 File system outputs: 32 92 Socket messages sent: 0 93 Socket messages received: 0 94 Signals delivered: 0 95 Page size (bytes): 4096 96 Exit status: 0