Add unconnected port options for Verilog netlist

[tjurtsch]

Description

This PR adds two options:

• post_synth_netlist_unconn_inputs {unconnected, nets, gnd, vcc}
• post_synth_netlist_unconn_outputs {unconnected, nets}

These options can be used to enforce how unconnected ports are treated in Verilog output. They can be tied to vcc, gnd, 1'bX (unconnected) or to a special net named __vpr__unconnXX (XX number is incremented to generate unique net for each port).

Related Issue

#1721

Motivation and Context

Previously unconnected input ports were always tied to 1'b0 and output ports were tied to a common net DummyOut which is incorrect.

How Has This Been Tested?

These options were tested with symbiflow-arch-defs
To reproduce the test, build the vpr end set env variable:

make -j `nproc`
export VPR=$PWD/build/vpr/vpr

Then, in a different directory, clone and build symbiflow-arch-defs:

git clone --recursive [email protected]:antmicro/symbiflow-arch-defs.git -b test-vpr-unconnected-ports
cd symbiflow-arch-defs
make -j `nproc` env

Run an example with unconnected ports

cd build/quicklogic/qlf_k4n8/tests/design_flow/and2
make -j `nproc` and2_test-umc22-adder_analysis

Check out resulting and2_post_synthesis.v file.

You can change post_synth_netlist_unconn options in quicklogic/qlf_k4n8/CMakeLists.txt file.

Types of changes

• Bug fix (change which fixes an issue)
• New feature (change which adds functionality)
• Breaking change (fix or feature that would cause existing functionality to change)

Checklist:

• My change requires a change to the documentation
• I have updated the documentation accordingly
• I have added tests to cover my changes
• All new and existing tests passed

[vaughnbetz]

The code looks good. My only suggestion is that this comment on how the special unconnected nets are named in this PR seems like it should be put in the code somewhere too (perhaps in create_unconn_net, if there isn't a comment on that function already):

They can be tied to vcc, gnd, 1'bX (unconnected) or to a special net named __vpr__unconnXX (XX number is incremented to generate unique net for each port)

I forced a kokoro restart since they didn't run. It also looks like the code needs to be run through make format before it can be merged.

[vaughnbetz]

yosys + odin failure is expected. @tjurtsch : can you do a make format to pass that test and add the comment I mention above? Then we can merge this.

[vaughnbetz]

@sfkhalid : can I get you to take over closing this out? I think you just need to do a make format on this and push it (I'll watch CI to check it all works).

[lpawelcz]

I've added explanation of the names of generated nets in help messages as well as documentation entry about the new command line options.
I also removed writing of the DummyOut wire in verilog netlist because it is now handled by new options.
Code was formatted and rebased onto newest master.
Those options will be very helpful in incoming PR that will take care of #1946

@sfkhalid could you please take a look at the updates and let me know if everything is OK here?

[vaughnbetz]

Kokoro looks like it got stuck; doing a force rerun. Other than that it looks good to merge to me.