Request: Add option for merging top module ports in post-layout Verilog netlist and SDF timing annotation files

[lpawelcz]

Proposed Behaviour

It would be nice to have an option that would enable VPR to write post-layout verilog and SDF timing files with multi-bit ports instead of single-bit ones in top modules.

Current Behaviour

Currently post-layout verilogs consist only of single-bit wires, including the top module IO ports, for example:

module top (
    input \clk ,
    output \led[0] ,
    output \led[1] ,
    output \led[2] ,
    output \led[3] 
);

Possible Solution

Using such option should enable VPR to modify written verilog or perhaps make VPR write another file (so it would write one with single-bit ports and the other with multi-bit ports)
The file with multi-bit ports could look like for example this one:

module top (
    input \clk ,
    output [3:0] led);

Context

This is used in SymbiFlow where post layout Verilog and SDF files are used to perform simulation to verify correctness of the implemented design against the original verilog source design. To do so it is required to have at least the same top module ports in Verilog files generated from VPR.