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tjurtschtjurtsch
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netlist_writer: verilog: handle the unconnected port setting
1 parent 743eed7 commit 4ef3a7c

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3 files changed

+56
-28
lines changed

3 files changed

+56
-28
lines changed

‎vpr/src/base/netlist_writer.cpp

Lines changed: 53 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -18,6 +18,7 @@
1818
#include "vtr_version.h"
1919

2020
#include "vpr_error.h"
21+
#include "vpr_types.h"
2122

2223
#include "netlist_walker.h"
2324
#include "netlist_writer.h"
@@ -110,7 +111,7 @@ std::string indent(size_t depth);
110111
double get_delay_ps(double delay_sec);
111112

112113
void print_blif_port(std::ostream& os, size_t& unconn_count, const std::string& port_name, const std::vector<std::string>& nets, int depth);
113-
void print_verilog_port(std::ostream& os, const std::string& port_name, const std::vector<std::string>& nets, PortType type, int depth);
114+
void print_verilog_port(std::ostream& os, size_t& unconn_count, const std::string& port_name, const std::vector<std::string>& nets, PortType type, int depth, struct t_analysis_opts& opts);
114115

115116
std::string create_unconn_net(size_t& unconn_count);
116117
std::string escape_verilog_identifier(const std::string id);
@@ -187,7 +188,7 @@ class Instance {
187188
virtual void print_blif(std::ostream& os, size_t& unconn_count, int depth = 0) = 0;
188189

189190
///@brief Print the current instanse in Verilog, see print_blif() for argument descriptions
190-
virtual void print_verilog(std::ostream& os, int depth = 0) = 0;
191+
virtual void print_verilog(std::ostream& os, size_t& unconn_count, int depth = 0) = 0;
191192

192193
///@brief Print the current instanse in SDF, see print_blif() for argument descriptions
193194
virtual void print_sdf(std::ostream& os, int depth = 0) = 0;
@@ -200,13 +201,15 @@ class LutInst : public Instance {
200201
LogicVec lut_mask, ///<The LUT mask representing the logic function
201202
std::string inst_name, ///<The name of this instance
202203
std::map<std::string, std::vector<std::string>> port_conns, ///<The port connections of this instance. Key: port name, Value: connected nets
203-
std::vector<Arc> timing_arc_values) ///<The timing arcs of this instance
204+
std::vector<Arc> timing_arc_values, ///<The timing arcs of this instance
205+
struct t_analysis_opts opts)
204206
: type_("LUT_K")
205207
, lut_size_(lut_size)
206208
, lut_mask_(lut_mask)
207209
, inst_name_(inst_name)
208210
, port_conns_(port_conns)
209-
, timing_arcs_(timing_arc_values) {
211+
, timing_arcs_(timing_arc_values)
212+
, opts_(opts) {
210213
}
211214

212215
//Accessors
@@ -215,7 +218,7 @@ class LutInst : public Instance {
215218
std::string type() { return type_; }
216219

217220
public: //Instance interface method implementations
218-
void print_verilog(std::ostream& os, int depth) override {
221+
void print_verilog(std::ostream& os, size_t& unconn_count, int depth) override {
219222
//Instantiate the lut
220223
os << indent(depth) << type_ << " #(\n";
221224

@@ -231,10 +234,10 @@ class LutInst : public Instance {
231234
VTR_ASSERT(port_conns_.count("out"));
232235
VTR_ASSERT(port_conns_.size() == 2);
233236

234-
print_verilog_port(os, "in", port_conns_["in"], PortType::INPUT, depth + 1);
237+
print_verilog_port(os, unconn_count, "in", port_conns_["in"], PortType::INPUT, depth + 1, opts_);
235238
os << ","
236239
<< "\n";
237-
print_verilog_port(os, "out", port_conns_["out"], PortType::OUTPUT, depth + 1);
240+
print_verilog_port(os, unconn_count, "out", port_conns_["out"], PortType::OUTPUT, depth + 1, opts_);
238241
os << "\n";
239242

240243
os << indent(depth) << ");\n\n";
@@ -376,6 +379,7 @@ class LutInst : public Instance {
376379
std::string inst_name_;
377380
std::map<std::string, std::vector<std::string>> port_conns_;
378381
std::vector<Arc> timing_arcs_;
382+
struct t_analysis_opts opts_;
379383
};
380384

381385
class LatchInst : public Instance {
@@ -462,7 +466,7 @@ class LatchInst : public Instance {
462466
os << "\n";
463467
}
464468

465-
void print_verilog(std::ostream& os, int depth = 0) override {
469+
void print_verilog(std::ostream& os, size_t& /*unconn_count*/, int depth = 0) override {
466470
//Currently assume a standard DFF
467471
VTR_ASSERT(type_ == Type::RISING_EDGE);
468472

@@ -560,7 +564,8 @@ class BlackBoxInst : public Instance {
560564
std::vector<Arc> timing_arcs, ///<Combinational timing arcs
561565
std::map<std::string, sequential_port_delay_pair> ports_tsu, ///<Port setup checks
562566
std::map<std::string, sequential_port_delay_pair> ports_thld, ///<Port hold checks
563-
std::map<std::string, sequential_port_delay_pair> ports_tcq) ///<Port clock-to-q delays
567+
std::map<std::string, sequential_port_delay_pair> ports_tcq, ///<Port clock-to-q delays
568+
struct t_analysis_opts opts)
564569
: type_name_(type_name)
565570
, inst_name_(inst_name)
566571
, params_(params)
@@ -570,7 +575,8 @@ class BlackBoxInst : public Instance {
570575
, timing_arcs_(timing_arcs)
571576
, ports_tsu_(ports_tsu)
572577
, ports_thld_(ports_thld)
573-
, ports_tcq_(ports_tcq) {}
578+
, ports_tcq_(ports_tcq)
579+
, opts_(opts) {}
574580

575581
void print_blif(std::ostream& os, size_t& unconn_count, int depth = 0) override {
576582
os << indent(depth) << ".subckt " << type_name_ << " \\"
@@ -613,7 +619,7 @@ class BlackBoxInst : public Instance {
613619
os << "\n";
614620
}
615621

616-
void print_verilog(std::ostream& os, int depth = 0) override {
622+
void print_verilog(std::ostream& os, size_t& unconn_count, int depth = 0) override {
617623
//Instance type
618624
os << indent(depth) << type_name_ << " #(\n";
619625

@@ -633,7 +639,7 @@ class BlackBoxInst : public Instance {
633639
for (auto iter = input_port_conns_.begin(); iter != input_port_conns_.end(); ++iter) {
634640
auto& port_name = iter->first;
635641
auto& nets = iter->second;
636-
print_verilog_port(os, port_name, nets, PortType::INPUT, depth + 1);
642+
print_verilog_port(os, unconn_count, port_name, nets, PortType::INPUT, depth + 1, opts_);
637643
if (!(iter == --input_port_conns_.end() && output_port_conns_.empty())) {
638644
os << ",";
639645
}
@@ -644,7 +650,7 @@ class BlackBoxInst : public Instance {
644650
for (auto iter = output_port_conns_.begin(); iter != output_port_conns_.end(); ++iter) {
645651
auto& port_name = iter->first;
646652
auto& nets = iter->second;
647-
print_verilog_port(os, port_name, nets, PortType::OUTPUT, depth + 1);
653+
print_verilog_port(os, unconn_count, port_name, nets, PortType::OUTPUT, depth + 1, opts_);
648654
if (!(iter == --output_port_conns_.end())) {
649655
os << ",";
650656
}
@@ -755,6 +761,7 @@ class BlackBoxInst : public Instance {
755761
std::map<std::string, sequential_port_delay_pair> ports_tsu_;
756762
std::map<std::string, sequential_port_delay_pair> ports_thld_;
757763
std::map<std::string, sequential_port_delay_pair> ports_tcq_;
764+
struct t_analysis_opts opts_;
758765
};
759766

760767
/**
@@ -793,11 +800,13 @@ class NetlistWriterVisitor : public NetlistVisitor {
793800
NetlistWriterVisitor(std::ostream& verilog_os, ///<Output stream for verilog netlist
794801
std::ostream& blif_os, ///<Output stream for blif netlist
795802
std::ostream& sdf_os, ///<Output stream for SDF
796-
std::shared_ptr<const AnalysisDelayCalculator> delay_calc)
803+
std::shared_ptr<const AnalysisDelayCalculator> delay_calc,
804+
struct t_analysis_opts opts)
797805
: verilog_os_(verilog_os)
798806
, blif_os_(blif_os)
799807
, sdf_os_(sdf_os)
800-
, delay_calc_(delay_calc) {
808+
, delay_calc_(delay_calc)
809+
, opts_(opts) {
801810
auto& atom_ctx = g_vpr_ctx.atom();
802811

803812
//Initialize the pin to tnode look-up
@@ -931,10 +940,11 @@ class NetlistWriterVisitor : public NetlistVisitor {
931940
}
932941

933942
//All the cell instances
943+
size_t unconn_count = 0;
934944
verilog_os_ << "\n";
935945
verilog_os_ << indent(depth + 1) << "//Cell instances\n";
936946
for (auto& inst : cell_instances_) {
937-
inst->print_verilog(verilog_os_, depth + 1);
947+
inst->print_verilog(verilog_os_, unconn_count, depth + 1);
938948
}
939949

940950
verilog_os_ << "\n";
@@ -1213,7 +1223,7 @@ class NetlistWriterVisitor : public NetlistVisitor {
12131223
port_conns["out"].push_back(net);
12141224
}
12151225

1216-
auto inst = std::make_shared<LutInst>(lut_size, lut_mask, inst_name, port_conns, timing_arcs);
1226+
auto inst = std::make_shared<LutInst>(lut_size, lut_mask, inst_name, port_conns, timing_arcs, opts_);
12171227

12181228
return inst;
12191229
}
@@ -1413,7 +1423,7 @@ class NetlistWriterVisitor : public NetlistVisitor {
14131423
}
14141424
}
14151425

1416-
return std::make_shared<BlackBoxInst>(type, inst_name, params, attrs, input_port_conns, output_port_conns, timing_arcs, ports_tsu, ports_thld, ports_tcq);
1426+
return std::make_shared<BlackBoxInst>(type, inst_name, params, attrs, input_port_conns, output_port_conns, timing_arcs, ports_tsu, ports_thld, ports_tcq, opts_);
14171427
}
14181428

14191429
///@brief Returns an Instance object representing a Multiplier
@@ -1509,7 +1519,7 @@ class NetlistWriterVisitor : public NetlistVisitor {
15091519

15101520
VTR_ASSERT(pb_graph_node->num_clock_ports == 0); //No clocks
15111521

1512-
return std::make_shared<BlackBoxInst>(type_name, inst_name, params, attrs, input_port_conns, output_port_conns, timing_arcs, ports_tsu, ports_thld, ports_tcq);
1522+
return std::make_shared<BlackBoxInst>(type_name, inst_name, params, attrs, input_port_conns, output_port_conns, timing_arcs, ports_tsu, ports_thld, ports_tcq, opts_);
15131523
}
15141524

15151525
///@brief Returns an Instance object representing an Adder
@@ -1609,7 +1619,7 @@ class NetlistWriterVisitor : public NetlistVisitor {
16091619
}
16101620
}
16111621

1612-
return std::make_shared<BlackBoxInst>(type_name, inst_name, params, attrs, input_port_conns, output_port_conns, timing_arcs, ports_tsu, ports_thld, ports_tcq);
1622+
return std::make_shared<BlackBoxInst>(type_name, inst_name, params, attrs, input_port_conns, output_port_conns, timing_arcs, ports_tsu, ports_thld, ports_tcq, opts_);
16131623
}
16141624

16151625
std::shared_ptr<Instance> make_blackbox_instance(const t_pb* atom) {
@@ -1747,7 +1757,7 @@ class NetlistWriterVisitor : public NetlistVisitor {
17471757
attrs[attr.first] = attr.second;
17481758
}
17491759

1750-
return std::make_shared<BlackBoxInst>(type_name, inst_name, params, attrs, input_port_conns, output_port_conns, timing_arcs, ports_tsu, ports_thld, ports_tcq);
1760+
return std::make_shared<BlackBoxInst>(type_name, inst_name, params, attrs, input_port_conns, output_port_conns, timing_arcs, ports_tsu, ports_thld, ports_tcq, opts_);
17511761
}
17521762

17531763
///@brief Returns the top level pb_route associated with the given pb
@@ -2067,14 +2077,15 @@ class NetlistWriterVisitor : public NetlistVisitor {
20672077
std::map<std::pair<ClusterBlockId, int>, tatum::NodeId> pin_id_to_tnode_lookup_;
20682078

20692079
std::shared_ptr<const AnalysisDelayCalculator> delay_calc_;
2080+
struct t_analysis_opts opts_;
20702081
};
20712082

20722083
//
20732084
// Externally Accessible Functions
20742085
//
20752086

20762087
///@brief Main routing for this file. See netlist_writer.h for details.
2077-
void netlist_writer(const std::string basename, std::shared_ptr<const AnalysisDelayCalculator> delay_calc) {
2088+
void netlist_writer(const std::string basename, std::shared_ptr<const AnalysisDelayCalculator> delay_calc, struct t_analysis_opts opts) {
20782089
std::string verilog_filename = basename + "_post_synthesis.v";
20792090
std::string blif_filename = basename + "_post_synthesis.blif";
20802091
std::string sdf_filename = basename + "_post_synthesis.sdf";
@@ -2087,7 +2098,7 @@ void netlist_writer(const std::string basename, std::shared_ptr<const AnalysisDe
20872098
std::ofstream blif_os(blif_filename);
20882099
std::ofstream sdf_os(sdf_filename);
20892100

2090-
NetlistWriterVisitor visitor(verilog_os, blif_os, sdf_os, delay_calc);
2101+
NetlistWriterVisitor visitor(verilog_os, blif_os, sdf_os, delay_calc, opts);
20912102

20922103
NetlistWalker nl_walker(visitor);
20932104

@@ -2159,7 +2170,7 @@ void print_blif_port(std::ostream& os, size_t& unconn_count, const std::string&
21592170
*
21602171
* Handles special cases like multi-bit and disconnected ports
21612172
*/
2162-
void print_verilog_port(std::ostream& os, const std::string& port_name, const std::vector<std::string>& nets, PortType type, int depth) {
2173+
void print_verilog_port(std::ostream& os, size_t& unconn_count, const std::string& port_name, const std::vector<std::string>& nets, PortType type, int depth, struct t_analysis_opts& opts) {
21632174
//Port name
21642175
os << indent(depth) << "." << port_name << "(";
21652176

@@ -2169,10 +2180,26 @@ void print_verilog_port(std::ostream& os, const std::string& port_name, const st
21692180
if (nets[0].empty()) {
21702181
//Disconnected
21712182
if (type == PortType::INPUT || type == PortType::CLOCK) {
2172-
os << "1'b0";
2183+
switch (opts.post_synth_netlist_unconn_input_handling) {
2184+
case e_post_synth_netlist_unconn_handling::GND:
2185+
os << "1'b0"; break;
2186+
case e_post_synth_netlist_unconn_handling::VCC:
2187+
os << "1'b1"; break;
2188+
case e_post_synth_netlist_unconn_handling::NETS:
2189+
os << create_unconn_net(unconn_count); break;
2190+
case e_post_synth_netlist_unconn_handling::UNCONNECTED:
2191+
default:
2192+
os << "1'bX";;
2193+
}
21732194
} else {
21742195
VTR_ASSERT(type == PortType::OUTPUT);
2175-
os << "DummyOut";
2196+
switch (opts.post_synth_netlist_unconn_output_handling) {
2197+
case e_post_synth_netlist_unconn_handling::NETS:
2198+
os << create_unconn_net(unconn_count); break;
2199+
case e_post_synth_netlist_unconn_handling::UNCONNECTED:
2200+
default:
2201+
os << "1'bX";;
2202+
}
21762203
}
21772204
} else {
21782205
//Connected

‎vpr/src/base/netlist_writer.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -15,6 +15,6 @@
1515
* All written filenames end in {basename}_post_synthesis.{fmt} where {basename} is the
1616
* basename argument and {fmt} is the file format (e.g. v, blif, sdf)
1717
*/
18-
void netlist_writer(const std::string basename, std::shared_ptr<const AnalysisDelayCalculator> delay_calc);
18+
void netlist_writer(const std::string basename, std::shared_ptr<const AnalysisDelayCalculator> delay_calc, struct t_analysis_opts opts);
1919

2020
#endif

‎vpr/src/base/vpr_api.cpp

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1279,7 +1279,8 @@ void vpr_analysis(t_vpr_setup& vpr_setup, const t_arch& Arch, const RouteStatus&
12791279

12801280
//Write the post-syntesis netlist
12811281
if (vpr_setup.AnalysisOpts.gen_post_synthesis_netlist) {
1282-
netlist_writer(atom_ctx.nlist.netlist_name().c_str(), analysis_delay_calc);
1282+
netlist_writer(atom_ctx.nlist.netlist_name().c_str(), analysis_delay_calc,
1283+
vpr_setup.AnalysisOpts);
12831284
}
12841285

12851286
//Do power analysis

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