Adding includes_dir and include_list_add to task config file

[sdamghan]

Description

1. includes_dir and include_list_add have been added to task config files as optional parameters. Users can pass additional (.v) or (.vh) files including some extra feature to the VTR flow.
2. A modified version of ch_intrinsics has been added to benchmarks without `define macros
3. New header files have added to cover the ch_intrinsics definitions
4. New test is added to vtr_reg_basic/no_timing to test the new feature

Usage:

• For run_vtr_flow users need to added the parameter -include 1.v 2.vh ...
• For run_vtr_task, includes_dir and include_list_add need to be specified in the task config.txt

Related Issue

PR #1753
PR #1774

Motivation and Context

Support a new feature to add separate files than the main circuit design to cover additional design supports like macro definitons

How Has This Been Tested?

run_vtr_task
run_vtr_flow
run_reg_test

Types of changes

• Bug fix (change which fixes an issue)
• New feature (change which adds functionality)
• Breaking change (fix or feature that would cause existing functionality to change)

Checklist:

• My change requires a change to the documentation
• I have updated the documentation accordingly
• I have added tests to cover my changes
• All new and existing tests passed

[vaughnbetz]

There are some CI failures.

1. Odin test failures:

• SIGABRT(134) . . . . . . . . . . . . large/matmul_8x8_fp16/k6_frac_N10_frac_chain_mem32K_40nm
  VB: out of memory or some such?
• Looks like the new ch_intrinsics_modified design failed:
  /tmpfs/src/github/vtr-verilog-to-routing/vtr_flow/benchmarks/verilog/ch_intrinsics_modified.v:135:1: warning[PARSE_TO_AST]: MEMORY_CONTROLLER_ADDR_SIZE define cannot be found, replacing with empty string and continuing synthesis
  133 | reg [31:0] var0;
  134 | reg [MEMORY_CONTROLLER_ADDR_SIZE-1:0] scevgep; 135 | reg [MEMORY_CONTROLLER_ADDR_SIZE-1:0] s_07;
  ^~~~
  136 | reg [31:0] indvar_next;
  137 | reg exitcond;
  Killed
  Odin exited with code: 137
  Elapsed Time: 422.18 Seconds
  CPU: 91%
  Max Memory: 106093408 KiB
  Average Memory: 0 KiB
  Minor PF: 28990317
  Major PF: 30843
  Context Switch: 498+31662
  Program Exit Code: 0

2. python lint failed.

• 2021-06-10T13:08:29.3577626Z ************* Module vtr.odin.odin
  2021-06-10T13:08:29.3579020Z vtr_flow/scripts/python_libs/vtr/odin/odin.py:11:0: C0116: Missing function or method docstring (missing-function-docstring)
  2021-06-10T13:08:29.3580539Z vtr_flow/scripts/python_libs/vtr/odin/odin.py:11:0: R0913: Too many arguments (7/5) (too-many-arguments)
  2021-06-10T13:08:29.3581849Z vtr_flow/scripts/python_libs/vtr/odin/odin.py:50:0: R0912: Too many branches (15/12) (too-many-branches)
  2021-06-10T13:08:29.3583037Z �[92mvtr_flow/scripts/python_libs/vtr/odin/init.py passed �[0m
  2021-06-10T13:08:29.3583853Z �[91mERROR: 3 file(s) failed lint test. �[0m

• 2021-06-10T13:08:29.3560084Z ************* Module vtr.task
  2021-06-10T13:08:29.3561074Z vtr_flow/scripts/python_libs/vtr/task.py:178:0: R0912: Too many branches (15/12) (too-many-branches)

• 2021-06-10T13:08:29.3533942Z ************* Module run_vtr_flow
  2021-06-10T13:08:29.3534958Z vtr_flow/scripts/run_vtr_flow.py:46:0: R0915: Too many statements (51/50) (too-many-statements)

[vaughnbetz]

The too many branches and too many statements lint errors are about long functions and would usually be fixed with helper functions, e.g.:

https://pycodequ.al/docs/pylint-messages/r0912-too-many-branches.html

[vaughnbetz]

Thanks for the enhanced comments. I have some additional feedback (not too big). Also, CI is failing so there seems to be an issue with the include files. E.g.

File "/home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing/vtr_flow/scripts/python_libs/vtr/task.py", line 462, in create_jobs
includes,
UnboundLocalError: local variable 'includes' referenced before assignment
Error: Process completed with exit code 1.

[sdamghan]

Anytime @vaughnbetz , thanks for your time providing good comments.
I have split the ch_intrinsic design into two header files (definitions), a sub-module Verilog file called memory_contorller and the top_module called ch_intrinsic_top. The good news is that now we support having a list of files for a single design using the include feature. Users can split their design into sub-modules and header files (for definitions and macros) and pass them as a single task to the VTR flow. I mention here again that the include files are shared among all benchmark circuits that have pros and cons. The main advantage is that users can have multiple shared designs (sub-modules) for different benchmarks' top modules, like RAM, SHIFT, etc. Moreover, each benchmark circuit can have its own variable sizes, like ADDR_WIDTH, and use shared sub-modules with their width. However, a disadvantage could be that once an include is specified in a task config file, it will be compiled with every single benchmark circuit that sometimes may result in having useless logic in the final netlist (it can be solved using `ifdef, though). If you have additional feedback please let me know, otherwise, the PR is ready for merge :)

Dear @aman26kbm , hoping this would ease the recent work for integrating the Koios benchmark in the VTR flow :) That would be great if you have the include feature tested with Koios circuits. Please let me know if you face any errors during this process.

[aman26kbm]

Thanks, @sdamghan . I'll use this for Koios when this PR gets merged and let you know if I face any issues :)

[vaughnbetz]

Looks good. One last typo to fix (flagged above) but that's not merge-gating (but good to fix after the merge if you don't get to it before).
I relaunched kokoro; the nightly tests should pass now.

[sdamghan]

CI passed successfully, merging to remove the barrier for Koios benchmark PR.