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[Infra]: - Adding a modified version of ch_intrinsics to benchmarks without `define macros
 - Adding header files to cover the ch_intrinsics definitons - Adding the new test to vtr_reg_basic/no_timing to test the new feature Signed-off-by: Seyed Alireza Damghani <[email protected]>
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‎vtr_flow/benchmarks/verilog/ch_intrinsics_modified.v

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/*
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* Definitons is to provide in ./include/generic_definitons.vh
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*/
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module memory_controller
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(
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clk,
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memory_controller_address,
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memory_controller_write_enable,
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memory_controller_in,
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memory_controller_out
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);
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input clk;
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input [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] memory_controller_address;
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input memory_controller_write_enable;
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input [`MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_in;
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output [`MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_out;
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reg [`MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_out;
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reg [4:0] str_address;
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reg str_write_enable;
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reg [7:0] str_in;
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wire [7:0] str_out;
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single_port_ram _str (
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.clk( clk ),
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.addr( str_address ),
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.we( str_write_enable ),
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.data( str_in ),
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.out( str_out )
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);
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wire tag;
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//must use all wires inside module.....
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assign tag = |memory_controller_address & |memory_controller_address & | memory_controller_in;
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reg [`MEMORY_CONTROLLER_TAG_SIZE-1:0] prevTag;
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always @(posedge clk)
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prevTag <= tag;
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always @( tag or memory_controller_address or memory_controller_write_enable or memory_controller_in)
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begin
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case(tag)
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1'b0:
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begin
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str_address = memory_controller_address[5-1+0:0];
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str_write_enable = memory_controller_write_enable;
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str_in[8-1:0] = memory_controller_in[8-1:0];
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end
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endcase
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case(prevTag)
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1'b0:
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memory_controller_out = str_out;
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endcase
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end
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endmodule
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module memset
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(
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clk,
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reset,
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start,
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finish,
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return_val,
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m,
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c,
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n,
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memory_controller_write_enable,
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memory_controller_address,
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memory_controller_in,
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memory_controller_out
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);
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output[`MEMORY_CONTROLLER_ADDR_SIZE-1:0] return_val;
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reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] return_val;
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input clk;
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input reset;
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input start;
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output finish;
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reg finish;
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input [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] m;
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input [31:0] c;
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input [31:0] n;
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output [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] memory_controller_address;
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reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] memory_controller_address;
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output memory_controller_write_enable;
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reg memory_controller_write_enable;
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output [`MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_in;
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reg [`MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_in;
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output [`MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_out;
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reg [3:0] cur_state;
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/*
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parameter Wait = 4'd0;
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parameter entry = 4'd1;
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parameter entry_1 = 4'd2;
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parameter entry_2 = 4'd3;
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parameter bb = 4'd4;
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parameter bb_1 = 4'd5;
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parameter bb1 = 4'd6;
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parameter bb1_1 = 4'd7;
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parameter bb_nph = 4'd8;
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parameter bb2 = 4'd9;
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parameter bb2_1 = 4'd10;
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parameter bb2_2 = 4'd11;
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parameter bb2_3 = 4'd12;
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parameter bb2_4 = 4'd13;
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parameter bb4 = 4'd14;
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*/
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memory_controller memtroll (clk,memory_controller_address, memory_controller_write_enable, memory_controller_in, memory_controller_out);
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reg [31:0] indvar;
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reg var1;
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reg [31:0] tmp;
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reg [31:0] tmp8;
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reg var2;
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reg [31:0] var0;
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reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] scevgep;
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reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] s_07;
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reg [31:0] indvar_next;
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reg exitcond;
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always @(posedge clk)
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if (reset)
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cur_state <= 4'b0000;
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else
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case(cur_state)
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4'b0000:
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begin
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finish <= 1'b0;
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if (start == 1'b1)
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cur_state <= 4'b0001;
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else
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cur_state <= 4'b0000;
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end
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4'b0001:
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begin
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var0 <= n & 32'b00000000000000000000000000000011;
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cur_state <= 4'b0010;
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end
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4'b0010:
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begin
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var1 <= 1'b0;
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var0 <= 32'b00000000000000000000000000000000;
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cur_state <= 4'b0011;
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end
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4'b0011:
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begin
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if (|var1) begin
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cur_state <= 4'b0110;
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end
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else
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begin
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cur_state <= 4'b0100;
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end
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end
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4'b0100:
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begin
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cur_state <= 4'b0101;
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end
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4'b0101:
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begin
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cur_state <= 4'b0110;
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end
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4'b0110:
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begin
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var2 <= | (n [31:4]);
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cur_state <= 4'b0111;
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end
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4'b0111:
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begin
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if (|var2)
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begin
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cur_state <= 4'b1110;
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end
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else
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begin
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cur_state <= 4'b1000;
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end
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end
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4'b1000:
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begin
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tmp <= n ;
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indvar <= 32'b00000000000000000000000000000000;
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cur_state <= 4'b1001;
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end
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4'b1001:
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begin
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cur_state <= 4'b1010;
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end
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4'b1010:
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begin
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tmp8 <= indvar;
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indvar_next <= indvar;
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cur_state <= 4'b1011;
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end
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4'b1011:
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begin
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scevgep <= (m & tmp8);
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exitcond <= (indvar_next == tmp);
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cur_state <= 4'b1100;
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end
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4'b1100:
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begin
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s_07 <= scevgep;
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cur_state <= 4'b1101;
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end
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4'b1101:
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begin
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if (exitcond)
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begin
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cur_state <= 4'b1110;
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end
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else
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begin
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indvar <= indvar_next;
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cur_state <= 4'b1001;
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end
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end
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4'b1110:
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begin
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return_val <= m;
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finish <= 1'b1;
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cur_state <= 4'b0000;
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end
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endcase
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always @(cur_state)
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begin
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case(cur_state)
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4'b1101:
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begin
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memory_controller_address = s_07;
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memory_controller_write_enable = 1'b1;
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memory_controller_in = c;
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end
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endcase
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end
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endmodule

‎vtr_flow/benchmarks/verilog/include/generic_definitions1.vh

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/*
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* DEFINITIONS
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*/
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`define MEMORY_CONTROLLER_ADDR_SIZE 32
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`define MEMORY_CONTROLLER_DATA_SIZE 32

‎vtr_flow/benchmarks/verilog/include/generic_definitions2.vh

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/*
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* DEFINITIONS
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*/
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`define MEMORY_CONTROLLER_TAGS 1
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`define MEMORY_CONTROLLER_TAG_SIZE 1
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`define TAG__str 1'b0

‎vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_no_timing/config/config.txt

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# Path to directory of circuits to use
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circuits_dir=benchmarks/verilog
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# Path to directory of includes circuits to use
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includes_dir=benchmarks/verilog/include
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# Path to directory of architectures to use
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archs_dir=arch/no_timing/memory_sweep
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# Add circuits to list to sweep
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circuit_list_add=ch_intrinsics_modified.v
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circuit_list_add=ch_intrinsics.v
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circuit_list_add=diffeq1.v
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circuit_list_add=single_wire.v
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circuit_list_add=single_ff.v
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# Add circuits to includes list to sweep
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include_list_add=generic_definitions1.vh
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include_list_add=generic_definitions2.vh
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# Add architectures to list to sweep
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arch_list_add=k4_N10_memSize16384_memData64.xml
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‎vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_no_timing/config/golden_results.txt

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arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time
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k4_N10_memSize16384_memData64.xml ch_intrinsics.v common 1.83 0.03 8960 4 0.21 -1 -1 36092 -1 -1 72 99 1 0 success v8.0.0-2985-gac43b6bd1-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-11-03T08:54:06 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/gold/vtr-verilog-to-routing 34468 99 130 378 508 1 260 302 13 13 169 clb auto 0.05 602 0.16 0.00 36 1421 8 3.33e+06 2.28e+06 481319. 2848.04 0.73
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k4_N10_memSize16384_memData64.xml diffeq1.v common 2.98 0.04 8784 23 0.24 -1 -1 34032 -1 -1 72 162 0 5 success v8.0.0-2985-gac43b6bd1-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-11-03T08:54:06 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/gold/vtr-verilog-to-routing 37256 162 96 1214 1147 1 676 335 13 13 169 clb auto 0.14 4543 0.24 0.00 50 10225 50 3.33e+06 2.61e+06 641417. 3795.37 1.46
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k4_N10_memSize16384_memData64.xml single_wire.v common 0.28 0.01 5576 1 0.01 -1 -1 29552 -1 -1 0 1 0 0 success v8.0.0-2985-gac43b6bd1-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-11-03T08:54:06 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/gold/vtr-verilog-to-routing 22644 1 1 1 2 0 1 2 3 3 9 -1 auto 0.00 2 0.00 0.00 2 1 1 30000 0 1489.46 165.495 0.00
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k4_N10_memSize16384_memData64.xml single_ff.v common 0.33 0.01 5472 1 0.01 -1 -1 29636 -1 -1 1 2 0 0 success v8.0.0-2985-gac43b6bd1-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-11-03T08:54:06 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/gold/vtr-verilog-to-routing 22508 2 1 3 4 1 3 4 3 3 9 -1 auto 0.00 4 0.00 0.00 16 5 1 30000 30000 2550.78 283.420 0.01
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arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time
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k4_N10_memSize16384_memData64.xml ch_intrinsics_modified.v common 1.25 0.02 9304 4 0.17 -1 -1 40268 -1 -1 72 99 1 0 success v8.0.0-3718-g24b43911e release IPO VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-5.8.0-55-generic x86_64 2021-06-09T22:40:32 CASA44 /home/casauser/Desktop/Repos/sdamghan/vtr_flow/scripts 29304 99 130 378 508 1 260 302 13 13 169 clb auto 0.03 602 0.13 0.00 36 1421 8 3.33e+06 2.28e+06 481319. 2848.04 0.42
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k4_N10_memSize16384_memData64.xml ch_intrinsics.v common 1.07 0.03 9232 4 0.17 -1 -1 40260 -1 -1 72 99 1 0 success v8.0.0-3718-g24b43911e release IPO VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-5.8.0-55-generic x86_64 2021-06-09T22:40:32 CASA44 /home/casauser/Desktop/Repos/sdamghan/vtr_flow/scripts 29276 99 130 378 508 1 260 302 13 13 169 clb auto 0.03 602 0.12 0.00 36 1421 8 3.33e+06 2.28e+06 481319. 2848.04 0.27
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k4_N10_memSize16384_memData64.xml diffeq1.v common 3.00 0.02 9076 23 0.22 -1 -1 38816 -1 -1 72 162 0 5 success v8.0.0-3718-g24b43911e release IPO VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-5.8.0-55-generic x86_64 2021-06-09T22:40:32 CASA44 /home/casauser/Desktop/Repos/sdamghan/vtr_flow/scripts 34108 162 96 1214 1147 1 676 335 13 13 169 clb auto 0.12 4543 0.20 0.00 52 9173 16 3.33e+06 2.61e+06 671819. 3975.26 1.70
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k4_N10_memSize16384_memData64.xml single_wire.v common 0.15 0.01 5700 1 0.00 -1 -1 33572 -1 -1 0 1 0 0 success v8.0.0-3718-g24b43911e release IPO VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-5.8.0-55-generic x86_64 2021-06-09T22:40:32 CASA44 /home/casauser/Desktop/Repos/sdamghan/vtr_flow/scripts 22540 1 1 1 2 0 1 2 3 3 9 -1 auto 0.00 2 0.00 0.00 2 1 1 30000 0 1489.46 165.495 0.00
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k4_N10_memSize16384_memData64.xml single_ff.v common 0.16 0.00 5732 1 0.00 -1 -1 33548 -1 -1 1 2 0 0 success v8.0.0-3718-g24b43911e release IPO VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-5.8.0-55-generic x86_64 2021-06-09T22:40:32 CASA44 /home/casauser/Desktop/Repos/sdamghan/vtr_flow/scripts 22516 2 1 3 4 1 3 4 3 3 9 -1 auto 0.00 4 0.00 0.00 16 5 1 30000 30000 2550.78 283.420 0.00

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