[Infra]: Adding include_list_add and include_dir (both optional) to task config file

Signed-off-by: Seyed Alireza Damghani <[email protected]>

Author: sdamghan

vtr_flow/scripts/python_libs/vtr/flow.py

@@ -34,6 +34,7 @@ def run(
     architecture_file,
     circuit_file,
     power_tech_file=None,
+    include_files=None,
     start_stage=VtrStage.ODIN,
     end_stage=VtrStage.VPR,
     command_runner=vtr.CommandRunner(),
@@ -167,6 +168,16 @@ def run(
     shutil.copy(str(circuit_file), str(circuit_copy))
     shutil.copy(str(architecture_file), str(architecture_copy))
 
+    # Extract includes path 
+    for include in include_files:
+        include_paths = str(include).split(" ")
+        # Copy given additional Verilog files
+        for include_path in include_paths:
+            include_file = vtr.util.verify_file(include_path, "Circuit")
+            include_copy = temp_dir / include_file.name
+            shutil.copy(str(include_path), str(include_copy))
+
+
     # There are multiple potential paths for the netlist to reach a tool
     # We initialize it here to the user specified circuit and let downstream
     # stages update it
@@ -179,6 +190,7 @@ def run(
         vtr.odin.run(
             architecture_copy,
             next_stage_netlist,
+            include_files,
             output_netlist=post_odin_netlist,
             command_runner=command_runner,
             temp_dir=temp_dir,

vtr_flow/scripts/python_libs/vtr/odin/odin.py

@@ -4,13 +4,54 @@
 import shutil
 from collections import OrderedDict
 from pathlib import Path
+import xml.etree.ElementTree as ET
 from vtr import file_replace, determine_memory_addr_width, verify_file, CommandRunner, paths
 
+# initializing the raw odin config file
+def init_config_file (
+    odin_config_full_path,
+    circuit_list,
+    architecture_file,
+    output_netlist,
+    memory_addr_width,
+    min_hard_mult_size,
+    min_hard_adder_size,
+):
+    # Update the config file
+    file_replace(
+        odin_config_full_path,
+        {
+            "YYY": architecture_file,
+            "ZZZ": output_netlist,
+            "PPP": memory_addr_width,
+            "MMM": min_hard_mult_size,
+            "AAA": min_hard_adder_size,
+        },
+    )
+
+
+    # loading the given config file
+    config_file = ET.parse(odin_config_full_path)
+    root = config_file.getroot()
+
+    # based on the base condfig file
+    verilog_files_tag = root.find("verilog_files")
+    #remove the template line XXX, verilog_files_tag [0] is a comment 
+    verilog_files_tag.remove(verilog_files_tag[0])
+    for circuit in circuit_list:
+        verilog_file = ET.SubElement(verilog_files_tag, "verilog_file")
+        verilog_file.tail = "\n\n\t" if (circuit == circuit_list[-1]) else "\n\n\t\t"
+        verilog_file.text = circuit
+        
+    # update the config file with new values
+    config_file.write(odin_config_full_path)
+
 
 # pylint: disable=too-many-arguments, too-many-locals
 def run(
     architecture_file,
     circuit_file,
+    include_files,
     output_netlist,
     command_runner=CommandRunner(),
     temp_dir=Path("."),
@@ -90,19 +131,28 @@ def run(
     odin_config_full_path = str(temp_dir / odin_config)
     shutil.copyfile(odin_base_config, odin_config_full_path)
 
-    # Update the config file
-    file_replace(
+
+    circuit_list = []
+    if include_files:
+        # Extract includes path 
+        for include in include_files:
+            include_paths = str(include).split(" ")
+            for include_path in include_paths:
+                include_file = verify_file(include_path, "Circuit")
+                circuit_list.append(include_file.name)            
+            
+    # append the main circuit design as the last one
+    circuit_list.append(circuit_file.name)
+
+    init_config_file(
         odin_config_full_path,
-        {
-            "XXX": circuit_file.name,
-            "YYY": architecture_file.name,
-            "ZZZ": output_netlist.name,
-            "PPP": determine_memory_addr_width(str(architecture_file)),
-            "MMM": min_hard_mult_size,
-            "AAA": min_hard_adder_size,
-        },
+        circuit_list,
+        architecture_file.name,
+        output_netlist.name,
+        determine_memory_addr_width(str(architecture_file)),
+        min_hard_mult_size,
+        min_hard_adder_size,
     )
-
     cmd = [odin_exec]
     use_odin_simulation = False
 

vtr_flow/scripts/python_libs/vtr/task.py

@@ -33,6 +33,8 @@ def __init__(
         circuit_list_add,
         arch_list_add,
         parse_file,
+        includes_dir=None,
+        include_list_add=None,
         second_parse_file=None,
         script_path=None,
         script_params=None,
@@ -53,6 +55,8 @@ def __init__(
         self.arch_dir = archs_dir
         self.circuits = circuit_list_add
         self.archs = arch_list_add
+        self.include_dir = includes_dir
+        self.includes = include_list_add
         self.parse_file = parse_file
         self.second_parse_file = second_parse_file
         self.script_path = script_path
@@ -82,6 +86,7 @@ def __init__(
         task_name,
         arch,
         circuit,
+        include,
         script_params,
         work_dir,
         run_command,
@@ -92,6 +97,7 @@ def __init__(
         self._task_name = task_name
         self._arch = arch
         self._circuit = circuit
+        self._include = include
         self._script_params = script_params
         self._run_command = run_command
         self._parse_command = parse_command
@@ -116,6 +122,12 @@ def circuit(self):
         return the circuit file name of the job
         """
         return self._circuit
+    
+    def include(self):
+        """
+        return the include circuits file name of the job
+        """
+        return self._include
 
     def script_params(self):
         """
@@ -174,6 +186,8 @@ def load_task_config(config_file):
     unique_keys = set(
         [
             "circuits_dir",
+            "includes_dir",
+            "include_list_add",
             "archs_dir",
             "additional_files",
             "parse_file",
@@ -207,7 +221,12 @@ def load_task_config(config_file):
         value = value.strip()
 
         if key in unique_keys:
-            if key not in key_values:
+            if key == "include_list_add":
+                if key not in key_values: 
+                    key_values[key] = [value]
+                else:
+                    key_values[key].append(value)
+            elif key not in key_values:
                 key_values[key] = value
             elif key == "parse_file":
                 key_values["second_parse_file"] = value
@@ -316,6 +335,16 @@ def create_jobs(args, configs, after_run=False):
             # Collect any extra script params from the config file
             cmd = [abs_circuit_filepath, abs_arch_filepath]
 
+            includes = ""
+            if config.includes:
+                cmd += ["-include"]
+                for include in config.includes:             
+                    abs_include_filepath = resolve_vtr_source_file(config, include, config.include_dir)
+                    delimiter = " " if (include != config.includes[-1]) else ""
+                    includes = includes + abs_include_filepath + delimiter
+
+            cmd += [includes]
+
             # Check if additional architectural data files are present
             if config.additional_files_list_add:
                 for additional_file in config.additional_files_list_add:
@@ -401,6 +430,7 @@ def create_jobs(args, configs, after_run=False):
                             args,
                             config,
                             circuit,
+                            includes,
                             arch,
                             value,
                             cmd,
@@ -418,6 +448,7 @@ def create_jobs(args, configs, after_run=False):
                         args,
                         config,
                         circuit,
+                        includes,
                         arch,
                         None,
                         cmd,
@@ -437,6 +468,7 @@ def create_job(
     args,
     config,
     circuit,
+    include,
     arch,
     param,
     cmd,
@@ -501,6 +533,7 @@ def create_job(
         config.task_name,
         arch,
         circuit,
+        include,
         param_string,
         work_dir + "/" + param_string,
         current_cmd,

vtr_flow/scripts/run_vtr_flow.py

@@ -322,6 +322,13 @@ def vtr_command_argparser(prog=None):
         dest="odin_config",
         help="Supplies Odin with a custom config file for optimizations.",
     )
+    odin.add_argument(
+        "-include",
+        nargs="*",
+        default=None,
+        dest="include_list_file",
+        help="List of additional Verilog files to each circuit.",
+    )
     #
     # VPR arguments
     #
@@ -423,6 +430,7 @@ def vtr_command_main(arg_list, prog=None):
             Path(args.architecture_file),
             Path(args.circuit_file),
             power_tech_file=args.power_tech,
+            include_files=args.include_list_file,
             temp_dir=temp_dir,
             start_stage=args.start,
             end_stage=args.end,