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[Infra]: - Adding a modified version of ch_intrinsics without `define macros
 - Adding header files to cover the ch_intrinsics definiton - Adding a new task, hdl_include, to validate the include capability for tasks config file Signed-off-by: Seyed Alireza Damghani <[email protected]>
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‎vtr_flow/benchmarks/hdl_include/ch_intrinsics_modified.v

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/*
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* Modified ch_intrinsic.v relies on definitons provided in
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* two header files located at:
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* vtr_flow/benchmark/hdl_include/include/generic_definitions1.vh
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* vtr_flow/benchmark/hdl_include/include/generic_definitions2.vh
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*
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* This test is modified to allow testing of run_vtr_task capability to
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* include additional files in a benchmark
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*/
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module memory_controller
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(
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clk,
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memory_controller_address,
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memory_controller_write_enable,
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memory_controller_in,
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memory_controller_out
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);
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input clk;
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input [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] memory_controller_address;
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input memory_controller_write_enable;
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input [`MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_in;
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output [`MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_out;
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reg [`MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_out;
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reg [4:0] str_address;
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reg str_write_enable;
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reg [7:0] str_in;
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wire [7:0] str_out;
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single_port_ram _str (
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.clk( clk ),
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.addr( str_address ),
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.we( str_write_enable ),
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.data( str_in ),
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.out( str_out )
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);
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wire tag;
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//must use all wires inside module.....
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assign tag = |memory_controller_address & |memory_controller_address & | memory_controller_in;
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reg [`MEMORY_CONTROLLER_TAG_SIZE-1:0] prevTag;
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always @(posedge clk)
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prevTag <= tag;
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always @( tag or memory_controller_address or memory_controller_write_enable or memory_controller_in)
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begin
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case(tag)
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1'b0:
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begin
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str_address = memory_controller_address[5-1+0:0];
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str_write_enable = memory_controller_write_enable;
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str_in[8-1:0] = memory_controller_in[8-1:0];
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end
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endcase
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case(prevTag)
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1'b0:
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memory_controller_out = str_out;
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endcase
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end
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endmodule
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module memset
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(
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clk,
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reset,
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start,
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finish,
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return_val,
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m,
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c,
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n,
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memory_controller_write_enable,
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memory_controller_address,
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memory_controller_in,
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memory_controller_out
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);
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output[`MEMORY_CONTROLLER_ADDR_SIZE-1:0] return_val;
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reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] return_val;
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input clk;
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input reset;
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input start;
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output finish;
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reg finish;
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input [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] m;
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input [31:0] c;
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input [31:0] n;
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output [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] memory_controller_address;
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reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] memory_controller_address;
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output memory_controller_write_enable;
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reg memory_controller_write_enable;
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output [`MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_in;
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reg [`MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_in;
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output [`MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_out;
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reg [3:0] cur_state;
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/*
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parameter Wait = 4'd0;
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parameter entry = 4'd1;
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parameter entry_1 = 4'd2;
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parameter entry_2 = 4'd3;
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parameter bb = 4'd4;
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parameter bb_1 = 4'd5;
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parameter bb1 = 4'd6;
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parameter bb1_1 = 4'd7;
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parameter bb_nph = 4'd8;
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parameter bb2 = 4'd9;
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parameter bb2_1 = 4'd10;
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parameter bb2_2 = 4'd11;
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parameter bb2_3 = 4'd12;
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parameter bb2_4 = 4'd13;
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parameter bb4 = 4'd14;
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*/
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memory_controller memtroll (clk,memory_controller_address, memory_controller_write_enable, memory_controller_in, memory_controller_out);
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reg [31:0] indvar;
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reg var1;
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reg [31:0] tmp;
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reg [31:0] tmp8;
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reg var2;
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reg [31:0] var0;
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reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] scevgep;
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reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] s_07;
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reg [31:0] indvar_next;
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reg exitcond;
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always @(posedge clk)
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if (reset)
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cur_state <= 4'b0000;
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else
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case(cur_state)
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4'b0000:
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begin
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finish <= 1'b0;
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if (start == 1'b1)
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cur_state <= 4'b0001;
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else
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cur_state <= 4'b0000;
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end
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4'b0001:
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begin
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var0 <= n & 32'b00000000000000000000000000000011;
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cur_state <= 4'b0010;
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end
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4'b0010:
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begin
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var1 <= 1'b0;
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var0 <= 32'b00000000000000000000000000000000;
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cur_state <= 4'b0011;
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end
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4'b0011:
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begin
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if (|var1) begin
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cur_state <= 4'b0110;
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end
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else
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begin
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cur_state <= 4'b0100;
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end
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end
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4'b0100:
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begin
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cur_state <= 4'b0101;
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end
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4'b0101:
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begin
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cur_state <= 4'b0110;
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end
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4'b0110:
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begin
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var2 <= | (n [31:4]);
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cur_state <= 4'b0111;
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end
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4'b0111:
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begin
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if (|var2)
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begin
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cur_state <= 4'b1110;
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end
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else
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begin
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cur_state <= 4'b1000;
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end
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end
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4'b1000:
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begin
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tmp <= n ;
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indvar <= 32'b00000000000000000000000000000000;
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cur_state <= 4'b1001;
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end
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4'b1001:
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begin
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cur_state <= 4'b1010;
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end
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4'b1010:
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begin
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tmp8 <= indvar;
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indvar_next <= indvar;
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cur_state <= 4'b1011;
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end
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4'b1011:
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begin
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scevgep <= (m & tmp8);
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exitcond <= (indvar_next == tmp);
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cur_state <= 4'b1100;
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end
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4'b1100:
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begin
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s_07 <= scevgep;
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cur_state <= 4'b1101;
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end
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4'b1101:
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begin
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if (exitcond)
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begin
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cur_state <= 4'b1110;
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end
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else
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begin
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indvar <= indvar_next;
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cur_state <= 4'b1001;
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end
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end
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4'b1110:
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begin
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return_val <= m;
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finish <= 1'b1;
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cur_state <= 4'b0000;
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end
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endcase
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always @(cur_state)
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begin
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case(cur_state)
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4'b1101:
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begin
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memory_controller_address = s_07;
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memory_controller_write_enable = 1'b1;
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memory_controller_in = c;
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end
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endcase
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end
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endmodule

‎vtr_flow/benchmarks/hdl_include/include/README.md

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# include files
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This folder contains _include_ files for running the modified version of ch_intrisinc.
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_include_ files can be either a Verilog file or a Verilog header file. The main point worth mentioning is that the union of include files and the primary circuit should not result in any conflict like having multiple top_modules or declaring different variables with the same name.
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To create a task config file, the syntax for _include_ files is pretty much like the circuits or architectures.
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In the beginning, _inlcudes_dir_, a path to _include_ files should be specified. In the following, specifiers include_add_list show the _include_ files with a relative path to the _includes_dir_ path.
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In the case of having multiple designs with multiple _include_ files, all _include_ files will be considered for each circuit design.
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___________________________hdl_include task config file____________________________
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##############################################
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\# Configuration file for running experiments
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##############################################
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\# Path to directory of circuits to use
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circuits_dir=benchmarks/hdl_include
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\# Path to directory of includes circuits to use
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includes_dir=benchmarks/hdl_include/include
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\# Path to directory of architectures to use
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archs_dir=arch/no_timing/memory_sweep
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\# Add circuits to list to sweep
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circuit_list_add=ch_intrinsics_modified.v
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\# Add circuits to includes list to sweep
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include_list_add=generic_definitions1.vh
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include_list_add=generic_definitions2.vh
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\# Add architectures to list to sweep
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arch_list_add=k4_N10_memSize16384_memData64.xml
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\# Parse info and how to parse
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parse_file=vpr_no_timing.txt
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\# How to parse QoR info
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qor_parse_file=qor_no_timing.txt
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\# Script parameters
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script_params_common=-track_memory_usage --timing_analysis off
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___________________________________________________________________________________

‎vtr_flow/benchmarks/hdl_include/include/generic_definitions1.vh

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/*
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* This header file provides definitions for ch_intrinsic_modified.v
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* located at:
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* vtr_flow/benchmarks/hdl_include/ch_intrinsic_modified.v
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*/
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`define MEMORY_CONTROLLER_ADDR_SIZE 32
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`define MEMORY_CONTROLLER_DATA_SIZE 32

‎vtr_flow/benchmarks/hdl_include/include/generic_definitions2.vh

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/*
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* This header file provides definitions for ch_intrinsic_modified.v
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* located at:
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* vtr_flow/benchmarks/hdl_include/ch_intrinsic_modified.v
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*/
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`define MEMORY_CONTROLLER_TAGS 1
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`define MEMORY_CONTROLLER_TAG_SIZE 1
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`define TAG__str 1'b0

‎vtr_flow/tasks/regression_tests/vtr_reg_basic/hdl_include/config/config.txt

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##############################################
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# Configuration file for running experiments
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##############################################
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# Path to directory of circuits to use
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circuits_dir=benchmarks/hdl_include
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# Path to directory of includes circuits to use
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includes_dir=benchmarks/hdl_include/include
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# Path to directory of architectures to use
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archs_dir=arch/no_timing/memory_sweep
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# Add circuits to list to sweep
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circuit_list_add=ch_intrinsics_modified.v
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# Add circuits to includes list to sweep
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include_list_add=generic_definitions1.vh
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include_list_add=generic_definitions2.vh
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# Add architectures to list to sweep
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arch_list_add=k4_N10_memSize16384_memData64.xml
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# Parse info and how to parse
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parse_file=vpr_no_timing.txt
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# How to parse QoR info
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qor_parse_file=qor_no_timing.txt
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# Script parameters
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script_params_common=-track_memory_usage --timing_analysis off

‎vtr_flow/tasks/regression_tests/vtr_reg_basic/task_list.txt

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regression_tests/vtr_reg_basic/basic_no_timing
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regression_tests/vtr_reg_basic/basic_timing
33
regression_tests/vtr_reg_basic/basic_timing_no_sdc
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regression_tests/vtr_reg_basic/hdl_include

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