Skip to content

SystemVerilog: add tests for const #785

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 1 commit into from
Oct 29, 2024
Merged

SystemVerilog: add tests for const #785

merged 1 commit into from
Oct 29, 2024

Conversation

kroening
Copy link
Member

This adds tests for 1800 2017 6.20.6 const.

This adds tests for 1800 2017 6.20.6 "const".
@kroening kroening marked this pull request as ready for review October 23, 2024 15:09
@tautschnig tautschnig merged commit a5c8dfe into main Oct 29, 2024
9 checks passed
@tautschnig tautschnig deleted the const2 branch October 29, 2024 12:37
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
Projects
None yet
Development

Successfully merging this pull request may close these issues.

2 participants