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Pull requests: diffblue/hw-cbmc

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Pull requests list

SVA: sequence() methods for first_match and throughout Verilog
#1169 opened Jun 23, 2025 by kroening Loading…
Avoid sva_sequence_matcht default constructor cleanup
#1168 opened Jun 23, 2025 by kroening Loading…
world-level BMC: implement two empty match rules engines Verilog
#1167 opened Jun 20, 2025 by kroening Loading…
rewrite SVA sequences Verilog
#1166 opened Jun 20, 2025 by kroening • Draft
SVA: parentheses around the arguments of ## Verilog
#1165 opened Jun 19, 2025 by kroening Loading…
word-level BMC: precondition for timeframe engines
#1164 opened Jun 19, 2025 by kroening Loading…
SMV: do not use parentheses around nullary operands of ! SMV
#1163 opened Jun 18, 2025 by kroening Loading…
SVA: replace sva_sequence_concatenation_exprt Verilog
#1162 opened Jun 17, 2025 by kroening Loading…
SVA: strengthen typing of sva_sequence_concatenation_exprt cleanup
#1161 opened Jun 17, 2025 by kroening • Draft
introduce SMV enumeration type SMV
#1154 opened Jun 12, 2025 by kroening • Draft
Verilog: $isunknown Verilog
#1149 opened Jun 9, 2025 by kroening Loading…
NeurIPS 2025 SystemVerilog benchmarks
#1147 opened Jun 6, 2025 by kroening Loading…
BMC: completeness thresholds larger than one engines
#1115 opened May 18, 2025 by kroening • Draft
SMV: bit selection operator SMV
#1113 opened May 18, 2025 by kroening • Draft
introduce verilog_sva_property_typet Verilog
#1081 opened Apr 23, 2025 by kroening • Draft
SMV: expression typechecker now post-traversal SMV
#1040 opened Mar 28, 2025 by kroening Loading…
2
SVA monitor engines Verilog
#1011 opened Feb 25, 2025 by kroening • Draft
SystemVerilog: --initial-zero Verilog
#1001 opened Feb 20, 2025 by kroening Loading…
6
SystemVerilog: interface instantiation Verilog
#972 opened Feb 6, 2025 by kroening • Draft
SystemVerilog: declarations in named blocks in tasks/functions Verilog
#970 opened Feb 6, 2025 by kroening • Draft
1
SystemVerilog: preserve scopes between compilation units Verilog
#963 opened Feb 4, 2025 by kroening • Draft
SystemVerilog: create identifier expressions in scanner Verilog
#953 opened Jan 29, 2025 by kroening • Draft
Add chipsalliance/sv-tests to CI
#939 opened Jan 17, 2025 by kroening • Draft
aval/bval lowering for reduction operators Verilog
#930 opened Jan 16, 2025 by kroening • Draft
vlindex: fix parsing for constraint_block
#924 opened Jan 6, 2025 by kroening • Draft
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