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Merge pull request #785 from diffblue/const2
SystemVerilog: add tests for `const`
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+27
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regression/verilog/const/const1.sv

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module main;
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module main(input i);
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// 1800 2017 6.20.6
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const bit my_true2 = 1;
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const var my_true3 = 1;
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const logic my_true4 = 1;
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// the value on the RHS does _not_ need to be constant
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const logic my_true4 = i;
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endmodule

regression/verilog/const/const2.desc

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KNOWNBUG
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const2.sv
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^EXIT=10$
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^SIGNAL=0$
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--
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^warning: ignoring
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--
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Should be rejected owing to assignment to const variable.

regression/verilog/const/const2.sv

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module main(input clk, input [31:0] data);
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// The value need not be constant.
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const reg [31:0] data_const = data;
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// 1800 2017 6.20.6
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always @(posedge clk)
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// But can't assign to it.
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data_const = 123;
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endmodule

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