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Merge pull request #786 from diffblue/expr2verilog-indexed-part-select
Verilog: fix string generated for indexed part select
2 parents 96d5018 + 1896ff0 commit 9b93b39

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src/verilog/expr2verilog.cpp

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@@ -793,6 +793,8 @@ expr2verilogt::resultt expr2verilogt::convert_indexed_part_select(
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else
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dest += '-';
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dest += ':';
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dest += convert_rec(src.width()).s;
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dest += ']';
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