SystemVerilog: final immediate assertions #594
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This introduces the assertion_item rule, and moves the rules for assertion_item_declaration into the right place, following 1800-2017.
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This adds SystemVerilog final immediate assertions and final static assertions.
Continuous assertions expect the definition of a clock, which is an ill-fit for combinational logic. This changes the assertions for combinational logic to use a final static assertion.
tautschnig
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Jul 15, 2024
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This adds SystemVerilog final immediate assertions.