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SystemVerilog: final immediate assertions
This adds SystemVerilog final immediate assertions.
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CORE
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immediate3.sv
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--bound 0
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^\[full_adder\.assert\.1\] always \(\{ full_adder\.carry, full_adder\.sum \}\) == full_adder\.a \+ full_adder\.b \+ full_adder\.c: PROVED up to bound 0$
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^EXIT=0$
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^SIGNAL=0$
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--
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^warning: ignoring
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--

regression/verilog/SVA/immediate3.sv

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module full_adder(input a, b, c, output sum, carry);
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assign sum = a ^ b ^ c;
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assign carry = a & b | (a ^ b) & c;
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always @(*)
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assert final({carry, sum} == a + b + c);
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endmodule

src/verilog/parser.y

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@@ -3099,6 +3099,13 @@ statement_brace:
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assertion_item:
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concurrent_assertion_item
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| deferred_immediate_assertion_item
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;
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deferred_immediate_assertion_item:
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deferred_immediate_assertion_statement
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| block_identifier TOK_COLON deferred_immediate_assertion_statement
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{ $$ = $3; }
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;
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procedural_assertion_statement:
@@ -3110,6 +3117,7 @@ procedural_assertion_statement:
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immediate_assertion_statement:
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simple_immediate_assertion_statement
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| deferred_immediate_assertion_statement
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;
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simple_immediate_assertion_statement:
@@ -3130,6 +3138,27 @@ simple_immediate_cover_statement: TOK_COVER '(' expression ')' action_block
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{ init($$, ID_verilog_immediate_cover); mto($$, $3); mto($$, $5); }
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;
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deferred_immediate_assertion_statement:
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deferred_immediate_assert_statement
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| deferred_immediate_assume_statement
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| deferred_immediate_cover_statement
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;
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deferred_immediate_assert_statement:
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TOK_ASSERT TOK_FINAL '(' expression ')' action_block
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{ init($$, ID_verilog_immediate_assert); mto($$, $4); mto($$, $6); }
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;
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deferred_immediate_assume_statement:
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TOK_ASSUME TOK_FINAL '(' expression ')' action_block
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{ init($$, ID_verilog_immediate_assume); mto($$, $4); mto($$, $6); }
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;
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deferred_immediate_cover_statement:
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TOK_COVER TOK_FINAL '(' expression ')' statement_or_null
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{ init($$, ID_verilog_immediate_cover); mto($$, $4); mto($$, $6); }
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;
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wait_statement: TOK_WAIT '(' expression ')' statement_or_null
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{ init($$, ID_wait); mto($$, $3); mto($$, $5); }
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;

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