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LUT element support #7
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base: fpga-interchange-baseline
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Signed-off-by: Maciej Kurc <[email protected]>
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Signed-off-by: Maciej Kurc <[email protected]>
Signed-off-by: Maciej Kurc <[email protected]>
Signed-off-by: Maciej Kurc <[email protected]>
Signed-off-by: Maciej Kurc <[email protected]>
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LGTM apart one small comment
namespace vtr { | ||
static char* stringf(const char* format, ...) { | ||
// Initial buffer | ||
const int initialSize = 80 + 1; | ||
char* str = (char*)vtr::malloc(initialSize); | ||
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// Init and copy args list | ||
va_list va1, va2; | ||
va_start(va1, format); | ||
va_copy(va2, va1); | ||
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// First attempt | ||
int len = vsnprintf(str, initialSize, format, va1); | ||
VTR_ASSERT(len >= 0); | ||
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// The buffer was too small | ||
if (len >= initialSize) { | ||
str = (char*)vtr::realloc((void*)str, len + 1); | ||
VTR_ASSERT(str != nullptr); | ||
len = vsnprintf(str, len + 1, format, va2); | ||
VTR_ASSERT(len >= 0); | ||
VTR_ASSERT(len <= len); | ||
} | ||
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// Cleanup | ||
va_end(va1); | ||
va_end(va2); | ||
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return str; | ||
} | ||
} // namespace vtr |
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I believe this should end up in libvtrutils (or sth similar)
I have added the changes from this PR to the one open upstream: verilog-to-routing#1937. I have adapted the changes to solve some issues with xc7 and nexus devices, for instance the fact that the LUT bels of the "memory" type SLICEs can have other BEL pins, not taken into account in the |
This PR adds support for LUT elements.
A LUT element is modeled as a pb_type with one mode per each LUT BEL from the element. This is suboptimal as it doesn't allow to pack eg. two smaller LUTs together into a fractuable LUT element but it is ok as a starting point for future improvements.
Each individual LUT (inside its mode) has two modes: one for a LUT-thru and another for the actual LUT bel.