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Fixes to FPGA interchange arch reader #20

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This PR fixes the FPGA inerchange arch reader:

  • Added ability to import sites with "pure" IOs (no IOB, .input/.output only)
  • Fixed memory allocation issues (leaks, mixing new with malloc etc.)
  • Fixed incorrect port/pin indexing when creating pb_types
  • Synchronized logical tile pin indexing with complex block pb_type indexing by building the former from information taken from the latter.

mkurc-ant added 5 commits May 27, 2022 13:14
…ility functions for dumping pb_type hierarchy as it is being built.

Signed-off-by: Maciej Kurc <[email protected]>
…ge architecture, added a function for checking correctness.

Signed-off-by: Maciej Kurc <[email protected]>
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Mostly LGTM. I have left one comment.

One question would be whether you have run a test to verify that the series7 architecture can be correctly parsed with these changes, specially regarding the pin mapping between log-tile and complex block.

Comment on lines +1553 to +1590
if (is_out) {
auto* omode = &pad->modes[mode_idx];
omode->name = vtr::strdup("opad");
omode->parent_pb_type = pad;
omode->index = mode_idx;

omode->num_pb_type_children = 1;
omode->pb_type_children = new t_pb_type[1];
auto* opad = &omode->pb_type_children[0];
opad->name = vtr::strdup("opad");
opad->num_pb = 1;
opad->parent_mode = omode;

num_ports = 1;
opad->num_ports = num_ports;
opad->ports = (t_port*)vtr::calloc(num_ports, sizeof(t_port));
opad->blif_model = vtr::strdup(MODEL_OUTPUT);
opad->model = get_model(arch_, std::string(MODEL_OUTPUT));

opad->ports[0] = get_generic_port(arch_, opad, IN_PORT, "outpad", MODEL_OUTPUT);

omode->num_interconnect = 1;
omode->interconnect = new t_interconnect[1];
auto* o_ic = &omode->interconnect[0];

std::string opad_istr = std::string(pad->name) + std::string(".") + ipin;
std::string opad_ostr = std::string(opad->name) + std::string(".outpad");
std::string o_ic_name = std::string(pad->name) + std::string("_") + std::string(opad->name);

o_ic->name = vtr::strdup(o_ic_name.c_str());
o_ic->type = DIRECT_INTERC;
o_ic->parent_mode_index = mode_idx;
o_ic->parent_mode = omode;
o_ic->input_string = vtr::strdup(opad_istr.c_str());
o_ic->output_string = vtr::strdup(opad_ostr.c_str());

mode_idx++;
}
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I wonder if this can actually be generalized somehow, so that we do not repeat code for both inp and out

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Yeah, so I haven't checked that on 7-series yet. I'll do that.

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Unfortunately it does not work on xc7 ... The problem is that sub_tile names do not match complex block names in some cases. I'm debugging why it happens.

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2 participants