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RR graph generation with constant networks #14

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@mtdudek mtdudek commented Jan 25, 2022 •
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Description

Related Issue

Motivation and Context

How Has This Been Tested?

Types of changes

  • Bug fix (change which fixes an issue)
  • New feature (change which adds functionality)
  • Breaking change (fix or feature that would cause existing functionality to change)

Checklist:

  • My change requires a change to the documentation
  • I have updated the documentation accordingly
  • I have added tests to cover my changes
  • All new and existing tests passed

@acomodi
Merge pull request verilog-to-routing#1937 from antmicro/acom/fpga-in…
44f9683 
…terchange-improve-arch-reading

FPGA Interchange: improve arch reader
@mtdudek mtdudek force-pushed the mdudek/fpga-interchange-rr-graph-gen+constants branch from 5d21ac7 to 81bc7fc Compare January 25, 2022 13:28
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@mtdudek
RR_graph building for fpga interchange
a686865 
Signed-off-by: Maciej Dudek <[email protected]>
@mtdudek
Small bug fixes
88ad457 
Signed-off-by: Maciej Dudek <[email protected]>
@mtdudek
Fixes in rr graph generation
0b8ce1d 
Code refactor

Signed-off-by: Maciej Dudek <[email protected]>
@mtdudek
Fix unit test as testarch has 2 lut bels
b857d2b 
Small improvements to RR graph generation

Signed-off-by: Maciej Dudek <[email protected]>
@mtdudek
Get Xilinx 7 series to work
b4e4653 
Signed-off-by: Maciej Dudek <[email protected]>
@mtdudek
Reducing rr_node and rr_edge count in fpga_interchange node translati…
dd0970b 
…on step

Combine node forest to single tree

Signed-off-by: Maciej Dudek <[email protected]>
@mtdudek
Add support for constant networks
f20cc06 
Update to new mainline

Signed-off-by: Maciej Dudek <[email protected]>
@mtdudek
Format code
e34657c 
Signed-off-by: Maciej Dudek <[email protected]>
@mtdudek
Squashed 'libs/EXTERNAL/libinterchange/' changes from 53e3feda4..54f6…
cfae510 
…208f3

54f6208f3 Merge pull request SymbiFlow#69 from antmicro/mdudel/fix_annotations
d8a0567a5 Fix annotations in DeviceResources

git-subtree-dir: libs/EXTERNAL/libinterchange
git-subtree-split: 54f6208f32e20b746863da6ea54e3051fc9a830e
@mtdudek
Update libinterchange
acda4a0 
libinterchange: Updating libs/EXTERNAL/libinterchange/ (external git subtree from https://github.com/chipsalliance/fpga-interchange-schema.git main)
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@mtdudek
Misc fixes and comments
9a5d200 
Signed-off-by: Maciej Dudek <[email protected]>
@mtdudek mtdudek force-pushed the mdudek/fpga-interchange-rr-graph-gen+constants branch 2 times, most recently from d9d0d38 to 7d87999 Compare January 29, 2022 03:17
@mtdudek mtdudek requested a review from acomodi February 4, 2022 08:21
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@mtdudek mtdudek force-pushed the mdudek/fpga-interchange-rr-graph-gen+constants branch from 7d87999 to 4b38adf Compare February 4, 2022 16:40
@mtdudek mtdudek requested a review from acomodi February 4, 2022 16:41
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