Move common code to fpga_interchange_arch_utils

Signed-off-by: Maciej Dudek <[email protected]>

Author: mtdudek

libs/libarchfpga/src/fpga_interchange_arch_utils.cpp

@@ -77,7 +77,29 @@ float get_corner_value(DeviceResources::Device::CornerModel::Reader model, const
     return 0.;
 }
 
-void fill_switch(t_rr_switch_inf& switch_,
+char* int_to_string(char* buff, int value) {
+    if (value < 10) {
+        return &(*buff = '0' + value) + 1;
+    } else {
+        return &(*int_to_string(buff, value / 10) = '0' + value % 10) + 1;
+    }
+}
+
+void pip_types(std::set<std::tuple<int, bool>>& seen,
+               DeviceResources::Device::Reader ar_) {
+    for (const auto& tile : ar_.getTileTypeList()) {
+        for (const auto& pip : tile.getPips()) {
+            if (pip.isPseudoCells())
+                continue;
+            seen.emplace(pip.getTiming(), pip.getBuffered21());
+            if (!pip.getDirectional()) {
+                seen.emplace(pip.getTiming(), pip.getBuffered20());
+            }
+        }
+    }
+}
+
+void fill_switch(t_arch_switch_inf* switch_,
                  float R,
                  float Cin,
                  float Cout,
@@ -87,13 +109,73 @@ void fill_switch(t_rr_switch_inf& switch_,
                  float buf_size,
                  char* name,
                  SwitchType type) {
-    switch_.R = R;
-    switch_.Cin = Cin;
-    switch_.Cout = Cout;
-    switch_.Cinternal = Cinternal;
-    switch_.Tdel = Tdel;
-    switch_.mux_trans_size = mux_trans_size;
-    switch_.buf_size = buf_size;
-    switch_.name = name;
-    switch_.set_type(type);
+    switch_->R = R;
+    switch_->Cin = Cin;
+    switch_->Cout = Cout;
+    switch_->Cinternal = Cinternal;
+    switch_->set_Tdel(t_arch_switch_inf::UNDEFINED_FANIN, Tdel);
+    switch_->mux_trans_size = mux_trans_size;
+    switch_->buf_size = buf_size;
+    switch_->name = name;
+    switch_->set_type(type);
+}
+
+void process_cell_bel_mappings(DeviceResources::Device::Reader ar_,
+                               std::unordered_map<uint32_t, std::set<t_bel_cell_mapping>>& bel_cell_mappings_,
+                               std::function<std::string(size_t)> str) {
+    auto primLib = ar_.getPrimLibs();
+    auto portList = primLib.getPortList();
+
+    for (auto cell_mapping : ar_.getCellBelMap()) {
+        size_t cell_name = cell_mapping.getCell();
+
+        int found_valid_prim = false;
+        for (auto primitive : primLib.getCellDecls()) {
+            bool is_prim = str(primitive.getLib()) == std::string("primitives");
+            bool is_cell = cell_name == primitive.getName();
+
+            bool has_inout = false;
+            for (auto port_idx : primitive.getPorts()) {
+                auto port = portList[port_idx];
+
+                if (port.getDir() == INOUT) {
+                    has_inout = true;
+                    break;
+                }
+            }
+
+            if (is_prim && is_cell && !has_inout) {
+                found_valid_prim = true;
+                break;
+            }
+        }
+
+        if (!found_valid_prim)
+            continue;
+
+        for (auto common_pins : cell_mapping.getCommonPins()) {
+            std::vector<std::pair<size_t, size_t>> pins;
+
+            for (auto pin_map : common_pins.getPins())
+                pins.emplace_back(pin_map.getCellPin(), pin_map.getBelPin());
+
+            for (auto site_type_entry : common_pins.getSiteTypes()) {
+                size_t site_type = site_type_entry.getSiteType();
+
+                for (auto bel : site_type_entry.getBels()) {
+                    t_bel_cell_mapping mapping;
+
+                    mapping.cell = cell_name;
+                    mapping.site = site_type;
+                    mapping.pins = pins;
+
+                    std::set<t_bel_cell_mapping> maps{mapping};
+                    auto res = bel_cell_mappings_.emplace(bel, maps);
+                    if (!res.second) {
+                        res.first->second.insert(mapping);
+                    }
+                }
+            }
+        }
+    }
 }

libs/libarchfpga/src/fpga_interchange_arch_utils.h

@@ -2,20 +2,39 @@
 #define FPGAINTERCHANGE_ARCH_UTILS_FILE_H
 
 #include "arch_types.h"
+#include "arch_util.h"
 #include "arch_error.h"
 #include "vtr_error.h"
+#include "vtr_util.h"
 
 #include "DeviceResources.capnp.h"
 #include "LogicalNetlist.capnp.h"
 #include "capnp/serialize.h"
 #include "capnp/serialize-packed.h"
 #include <fcntl.h>
 #include <unistd.h>
+#include <set>
+#include <string>
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
+// Necessary to reduce code verbosity when getting the pin directions
+static const auto INPUT = LogicalNetlist::Netlist::Direction::INPUT;
+static const auto OUTPUT = LogicalNetlist::Netlist::Direction::OUTPUT;
+static const auto INOUT = LogicalNetlist::Netlist::Direction::INOUT;
+
+struct t_bel_cell_mapping {
+    size_t cell;
+    size_t site;
+    std::vector<std::pair<size_t, size_t>> pins;
+
+    bool operator<(const t_bel_cell_mapping& other) const {
+        return cell < other.cell || (cell == other.cell && site < other.site);
+    }
+};
+
 /****************** Utility functions ******************/
 
 /**
@@ -34,7 +53,20 @@ extern "C" {
 
 float get_corner_value(DeviceResources::Device::CornerModel::Reader model, const char* speed_model, const char* value);
 
-void fill_switch(t_rr_switch_inf& switch_,
+char* int_to_string(char* buff, int value);
+
+void pip_types(std::set<std::tuple<int, bool>>& seen,
+               DeviceResources::Device::Reader ar_);
+
+void process_cell_bel_mappings(DeviceResources::Device::Reader ar_,
+                               std::unordered_map<uint32_t, std::set<t_bel_cell_mapping>>& bel_cell_mappings_,
+                               std::function<std::string(size_t)> str);
+
+#ifdef __cplusplus
+}
+#endif
+template<typename T>
+void fill_switch(T* switch_,
                  float R,
                  float Cin,
                  float Cout,
@@ -45,8 +77,22 @@ void fill_switch(t_rr_switch_inf& switch_,
                  char* name,
                  SwitchType type);
 
-#ifdef __cplusplus
-}
-#endif
+void fill_switch(t_arch_switch_inf* switch_,
+                 float R,
+                 float Cin,
+                 float Cout,
+                 float Cinternal,
+                 float Tdel,
+                 float mux_trans_size,
+                 float buf_size,
+                 char* name,
+                 SwitchType type);
+
+template<typename T1, typename T2>
+void process_switches_array(DeviceResources::Device::Reader ar_,
+                            std::set<std::tuple<int, bool>>& seen,
+                            T1 switch_array,
+                            std::vector<std::tuple<std::tuple<int, bool>, int>>& pips_models_);
 
+#include "fpga_interchange_arch_utils.impl.h"
 #endif

libs/libarchfpga/src/fpga_interchange_arch_utils.impl.h

@@ -0,0 +1,94 @@
+/****************** Utility functions ******************/
+
+/**
+ * @brief The FPGA interchange timing model includes three different corners (min, typ and max) for each of the two
+ * speed_models (slow and fast).
+ *
+ * Timing data can be found on PIPs, nodes, site pins and bel pins.
+ * This function retrieves the timing value based on the wanted speed model and the wanted corner.
+ *
+ * Corner model is considered valid if at least one configuration is set.
+ * In that case this value shall be returned.
+ *
+ * More information on the FPGA Interchange timing model can be found here:
+ *   - https://github.com/chipsalliance/fpga-interchange-schema/blob/main/interchange/DeviceResources.capnp
+ */
+
+template<typename T>
+void fill_switch(T* switch_,
+                 float R,
+                 float Cin,
+                 float Cout,
+                 float Cinternal,
+                 float Tdel,
+                 float mux_trans_size,
+                 float buf_size,
+                 char* name,
+                 SwitchType type) {
+    switch_->R = R;
+    switch_->Cin = Cin;
+    switch_->Cout = Cout;
+    switch_->Cinternal = Cinternal;
+    switch_->Tdel = Tdel;
+    switch_->mux_trans_size = mux_trans_size;
+    switch_->buf_size = buf_size;
+    switch_->name = name;
+    switch_->set_type(type);
+}
+
+template<typename T1, typename T2>
+void process_switches_array(DeviceResources::Device::Reader ar_,
+                            std::set<std::tuple<int, bool>>& seen,
+                            T1 switch_array,
+                            std::vector<std::tuple<std::tuple<int, bool> ,int>>& pips_models_) {
+
+    fill_switch(&switch_array[T2(0)], 0, 0, 0, 0, 0, 0, 0,
+                vtr::strdup("short"), SwitchType::SHORT);
+    fill_switch(&switch_array[T2(1)], 0, 0, 0, 0, 0, 0, 0,
+                vtr::strdup("generic"), SwitchType::MUX);
+
+    const auto& pip_models = ar_.getPipTimings();
+    float R, Cin, Cout, Cint, Tdel;
+    std::string switch_name;
+    SwitchType type;
+    int id =2;
+    for (const auto& value : seen) {
+        int timing_model_id;
+        int mux_trans_size;
+        bool buffered;
+        std::tie(timing_model_id, buffered) = value;
+        const auto& model = pip_models[timing_model_id];
+        pips_models_.emplace_back(std::make_tuple(value, id));
+
+        R = Cin = Cint = Cout = Tdel = 0.0;
+        std::stringstream name;
+        std::string mux_type_string = buffered ? "mux_" : "passGate_";
+        name << mux_type_string;
+
+        R = get_corner_value(model.getOutputResistance(), "slow", "min");
+        name << "R" << std::scientific << R;
+
+        Cin = get_corner_value(model.getInputCapacitance(), "slow", "min");
+        name << "Cin" << std::scientific << Cin;
+
+        Cout = get_corner_value(model.getOutputCapacitance(), "slow", "min");
+        name << "Cout" << std::scientific << Cout;
+
+        if (buffered) {
+            Cint = get_corner_value(model.getInternalCapacitance(), "slow", "min");
+            name << "Cinternal" << std::scientific << Cint;
+        }
+
+        Tdel = get_corner_value(model.getInternalDelay(), "slow", "min");
+        name << "Tdel" << std::scientific << Tdel;
+
+        switch_name = name.str();
+        type = buffered ? SwitchType::MUX : SwitchType::PASS_GATE;
+        mux_trans_size = buffered ? 1 : 0;
+
+        fill_switch(&switch_array[T2(id)], R, Cin, Cout, Cint, Tdel,
+                    mux_trans_size, 0, vtr::strdup(switch_name.c_str()), type);
+
+        id++;
+    }
+}