DNM: Review Only - Add explicit ports

[litghost]

This PR adds a feature to enable explicit relationship between ports on a physical tile and the ports of the interior logical tile. This provides a way to solve part 1 of verilog-to-routing#1063

In a converstation with the VTR devs this is not a direction they want to go, but it is an expedient solution for the capacity issue f4pga/f4pga-arch-defs#1183 until the suggested method is added (stacks of physical tiles).

This PR is to get initial review on the explicit ports change, which will then be followed up with a wip/ branch, and a new master+wip PR.

[acomodi]

LGTM.
As far as I understood, with this patch, we need to add the information on the pin mapping to the pin_mapping of the equivalent site.

One thing I did not grasp is the following though. The IO of the physical tile are going to be all of them (e.g. in case of the BUFG all 16 instances) or only the reduced ones (input and output specified only once)?

[litghost]

we need to add the information on the pin mapping to the pin_mapping of the equivalent site.

Yes

One thing I did not grasp is the following though

The ports on the physical tiles need to be enough for all instances within the tile. Basically rather than specifying N pins and then duplicating them times capacity (total pins = N pins * N capacity), instead all tile pins must be explicitly specified. Then if the logical tiles have N logical pins, there must be at least total pins = N logical pins * N capacity, and that many direct specifications.