DNM: Review Only - Add explicit ports

libs/libarchfpga/src/physical_types.cpp

@@ -110,7 +110,12 @@ std::vector<int> t_physical_tile_type::get_clock_pins_indices() const {
     int clock_pins_start_idx = 0;
     int clock_pins_stop_idx = 0;
 
-    for (int capacity_num = 0; capacity_num < this->capacity; capacity_num++) {
+    int num_capacity = 1;
+    if (capacity_type == e_capacity_type::DUPLICATE) {
+        num_capacity = this->capacity;
+    }
+
+    for (int capacity_num = 0; capacity_num < num_capacity; capacity_num++) {
         // Ranges are picked on the basis that pins are ordered: inputs, outputs, then clock pins
         // This is because ProcessPb_type assigns pb_type port indices in that order and
         // SetupPinLocationsAndPinClasses assigns t_logical_block_type_ptr pin indices in the order of port indices

libs/libarchfpga/src/physical_types.h

@@ -523,6 +523,12 @@ enum class e_sb_type {
 
 };
 
+enum class e_capacity_type {
+    DUPLICATE, // Capacity duplicates ports.
+    EXPLICIT   // Capacity increases the number of logical tiles, but does not
+               // modify the physical ports.
+};
+
 constexpr int NO_SWITCH = -1;
 constexpr int DEFAULT_SWITCH = -2;
 
@@ -577,6 +583,7 @@ struct t_physical_tile_type {
     int num_clock_pins = 0;
 
     int capacity = 0;
+    e_capacity_type capacity_type = e_capacity_type::DUPLICATE;
 
     int width = 0;
     int height = 0;
@@ -625,18 +632,20 @@ struct t_physical_tile_type {
  *  vtr::bimap container.
  */
 struct t_logical_pin {
+    int z_index = -1;
     int pin = -1;
 
-    t_logical_pin(int value) {
+    t_logical_pin(int z_index_value, int value) {
+        z_index = z_index_value;
         pin = value;
     }
 
     bool operator==(const t_logical_pin o) const {
-        return pin == o.pin;
+        return z_index == o.z_index && pin == o.pin;
     }
 
     bool operator<(const t_logical_pin o) const {
-        return pin < o.pin;
+        return std::make_pair(z_index, pin) < std::make_pair(o.z_index, o.pin);
     }
 };
 

vpr/src/base/ShowSetup.cpp

@@ -79,7 +79,7 @@ void printClusteredNetlistStats() {
         num_blocks_type[logical_block->index]++;
         if (is_io_type(physical_tile)) {
             for (j = 0; j < logical_block->pb_type->num_pins; j++) {
-                int physical_pin = get_physical_pin(physical_tile, logical_block, j);
+                int physical_pin = get_physical_pin(physical_tile, /*z_index=*/0, logical_block, j);
                 auto pin_class = physical_tile->pin_class[physical_pin];
                 auto class_inf = physical_tile->class_inf[pin_class];
 

vpr/src/base/check_netlist.cpp

@@ -95,7 +95,7 @@ static int check_connections_to_global_clb_pins(ClusterNetId net_id, int verbosi
         auto physical_type = pick_best_physical_type(logical_type);
 
         int log_index = cluster_ctx.clb_nlist.pin_logical_index(pin_id);
-        int pin_index = get_physical_pin(physical_type, logical_type, log_index);
+        int pin_index = get_physical_pin(physical_type, /*z_index=*/0, logical_type, log_index);
 
         if (physical_type->is_ignored_pin[pin_index] != net_is_ignored
             && !is_io_type(physical_type)) {

vpr/src/base/read_netlist.cpp

@@ -951,7 +951,7 @@ static void load_external_nets_and_cb(ClusteredNetlist& clb_nlist) {
         block_type = clb_nlist.block_type(blk_id);
         auto tile_type = pick_best_physical_type(block_type);
         for (j = 0; j < block_type->pb_type->num_pins; j++) {
-            int physical_pin = get_physical_pin(tile_type, block_type, j);
+            int physical_pin = get_physical_pin(tile_type, /*z_index=*/0, block_type, j);
 
             //Iterate through each pin of the block, and see if there is a net allocated/used for it
             clb_net_id = clb_nlist.block_net(blk_id, j);
@@ -1001,7 +1001,7 @@ static void load_external_nets_and_cb(ClusteredNetlist& clb_nlist) {
             block_type = clb_nlist.block_type(clb_nlist.pin_block(pin_id));
             auto tile_type = pick_best_physical_type(block_type);
             int logical_pin = clb_nlist.pin_logical_index(pin_id);
-            int physical_pin = get_physical_pin(tile_type, block_type, logical_pin);
+            int physical_pin = get_physical_pin(tile_type, /*z_index=*/0, block_type, logical_pin);
 
             if (tile_type->is_ignored_pin[physical_pin] != is_ignored_net) {
                 VTR_LOG_WARN(

vpr/src/base/read_route.cpp

@@ -23,6 +23,7 @@
 #include "rr_graph.h"
 #include "vtr_assert.h"
 #include "vtr_util.h"
+#include "vtr_time.h"
 #include "tatum/echo_writer.hpp"
 #include "vtr_log.h"
 #include "check_route.h"
@@ -40,6 +41,7 @@
 #include "echo_files.h"
 #include "route_common.h"
 #include "read_route.h"
+#include "rr_graph2.h"
 
 /*************Functions local to this module*************/
 static void process_route(std::ifstream& fp, const char* filename, int& lineno);
@@ -192,7 +194,7 @@ static void process_nets(std::ifstream& fp, ClusterNetId inet, std::string name,
 static void process_nodes(std::ifstream& fp, ClusterNetId inet, const char* filename, int& lineno) {
     /* Not a global net. Goes through every node and add it into trace.head*/
 
-    auto& cluster_ctx = g_vpr_ctx.mutable_clustering();
+    auto& cluster_ctx = g_vpr_ctx.clustering();
     auto& device_ctx = g_vpr_ctx.mutable_device();
     auto& route_ctx = g_vpr_ctx.mutable_routing();
     auto& place_ctx = g_vpr_ctx.placement();
@@ -206,6 +208,45 @@ static void process_nodes(std::ifstream& fp, ClusterNetId inet, const char* file
     std::string input;
     std::vector<std::string> tokens;
 
+    // Build lookup from SOURCE/SINK node to ClusterBlockId.
+    std::unordered_map<int, ClusterBlockId> node_to_block;
+
+    {
+        vtr::ScopedStartFinishTimer timer("Building ClusterBlockId lookup");
+
+        for (auto net_id : cluster_ctx.clb_nlist.nets()) {
+            int pin_count = 0;
+            for (auto pin_id : cluster_ctx.clb_nlist.net_pins(net_id)) {
+                auto block_id = cluster_ctx.clb_nlist.pin_block(pin_id);
+
+                const auto* logical_tile = cluster_ctx.clb_nlist.block_type(block_id);
+                const auto* physical_tile = physical_tile_type(block_id);
+                VTR_ASSERT(block_id);
+                int i = place_ctx.block_locs[block_id].loc.x;
+                int j = place_ctx.block_locs[block_id].loc.y;
+
+                int logical_pin_index = cluster_ctx.clb_nlist.pin_logical_index(pin_id);
+                int physical_pin_index = get_physical_pin(
+                    physical_tile, place_ctx.block_locs[block_id].loc.z,
+                    logical_tile, logical_pin_index);
+                int physical_pin_class = physical_tile->pin_class[physical_pin_index];
+                int class_inode = get_rr_node_index(device_ctx.rr_node_indices,
+                                                    i, j, (pin_count == 0 ? SOURCE : SINK), /* First pin is driver */
+                                                    physical_pin_class);
+
+                auto result = node_to_block.insert(std::make_pair(class_inode, block_id));
+                if (!result.second && result.first->second != block_id) {
+                    vpr_throw(VPR_ERROR_ROUTE, filename, lineno,
+                              "Clustered netlist has inconsistent rr node mapping, class rr node %d has two block ids %zu and %zu?",
+                              class_inode, (size_t)block_id, result.first->second);
+                }
+                pin_count++;
+            }
+        }
+
+        VTR_LOG("ClusterBlockId lookup has %zu entries\n", node_to_block.size());
+    }
+
     /*Walk through every line that begins with Node:*/
     while (std::getline(fp, input)) {
         ++lineno;
@@ -285,9 +326,22 @@ static void process_nodes(std::ifstream& fp, ClusterNetId inet, const char* file
             if (tokens[6 + offset] != "Switch:") {
                 /*This is an opin or ipin, process its pin nums*/
                 if (!is_io_type(device_ctx.grid[x][y].type) && (tokens[2] == "IPIN" || tokens[2] == "OPIN")) {
+                    // Convert this IPIN/OPIN back to class.
+                    auto rr_type = device_ctx.rr_nodes[inode].type();
+                    VTR_ASSERT(rr_type == IPIN || rr_type == OPIN);
                     int pin_num = device_ctx.rr_nodes[inode].ptc_num();
-                    int height_offset = device_ctx.grid[x][y].height_offset;
-                    ClusterBlockId iblock = place_ctx.grid_blocks[x][y - height_offset].blocks[0];
+                    int iclass = device_ctx.grid[x][y].type->pin_class[pin_num];
+                    int class_inode = get_rr_node_index(device_ctx.rr_node_indices,
+                                                        x, y, (rr_type == OPIN ? SOURCE : SINK), iclass);
+
+                    auto itr = node_to_block.find(class_inode);
+                    if (itr == node_to_block.end()) {
+                        vpr_throw(VPR_ERROR_ROUTE, filename, lineno,
+                                  "Class RR node %d does not have an associated ClusterBlockId?", class_inode);
+                    }
+
+                    ClusterBlockId iblock = itr->second;
+                    VTR_ASSERT(iblock);
                     t_pb_graph_pin* pb_pin = get_pb_graph_node_pin_from_block_pin(iblock, pin_num);
                     t_pb_type* pb_type = pb_pin->parent_node->pb_type;
 

vpr/src/base/vpr_context.h

@@ -286,6 +286,7 @@ struct RoutingContext : public Context {
     vtr::vector<ClusterNetId, std::unordered_set<int>> trace_nodes;
 
     vtr::vector<ClusterNetId, std::vector<int>> net_rr_terminals; /* [0..num_nets-1][0..num_pins-1] */
+    std::unordered_map<int, ClusterBlockId> rr_net_map;
 
     vtr::vector<ClusterBlockId, std::vector<int>> rr_blk_source; /* [0..num_blocks-1][0..num_class-1] */
 

vpr/src/draw/draw.cpp

@@ -2661,7 +2661,7 @@ void draw_highlight_blocks_color(t_logical_block_type_ptr type, ClusterBlockId b
             continue;
 
         auto physical_tile = physical_tile_type(blk_id);
-        int physical_pin = get_physical_pin(physical_tile, type, k);
+        int physical_pin = get_physical_pin(physical_tile, /*z_index=*/0, type, k);
 
         iclass = physical_tile->pin_class[physical_pin];
 

vpr/src/pack/output_clustering.cpp

@@ -66,7 +66,7 @@ static void print_stats() {
         auto logical_block = cluster_ctx.clb_nlist.block_type(blk_id);
         auto physical_tile = pick_best_physical_type(logical_block);
         for (ipin = 0; ipin < logical_block->pb_type->num_pins; ipin++) {
-            int physical_pin = get_physical_pin(physical_tile, logical_block, ipin);
+            int physical_pin = get_physical_pin(physical_tile, /*z_index=*/0, logical_block, ipin);
             auto pin_class = physical_tile->pin_class[physical_pin];
             auto pin_class_inf = physical_tile->class_inf[pin_class];
 

vpr/src/place/place_macro.cpp

@@ -82,7 +82,7 @@ static void find_all_the_macro(int* num_of_macro, std::vector<ClusterBlockId>& p
 
         num_blk_pins = cluster_ctx.clb_nlist.block_type(blk_id)->pb_type->num_pins;
         for (to_iblk_pin = 0; to_iblk_pin < num_blk_pins; to_iblk_pin++) {
-            int to_physical_pin = get_physical_pin(physical_tile, logical_block, to_iblk_pin);
+            int to_physical_pin = get_physical_pin(physical_tile, /*z_index=*/0, logical_block, to_iblk_pin);
 
             to_net_id = cluster_ctx.clb_nlist.block_net(blk_id, to_iblk_pin);
             to_idirect = f_idirect_from_blk_pin[physical_tile->index][to_physical_pin];
@@ -102,7 +102,7 @@ static void find_all_the_macro(int* num_of_macro, std::vector<ClusterBlockId>& p
                     || (is_constant_clb_net(to_net_id)
                         && !net_is_driven_by_direct(to_net_id)))) {
                 for (from_iblk_pin = 0; from_iblk_pin < num_blk_pins; from_iblk_pin++) {
-                    int from_physical_pin = get_physical_pin(physical_tile, logical_block, from_iblk_pin);
+                    int from_physical_pin = get_physical_pin(physical_tile, /*z_index=*/0, logical_block, from_iblk_pin);
 
                     from_net_id = cluster_ctx.clb_nlist.block_net(blk_id, from_iblk_pin);
                     from_idirect = f_idirect_from_blk_pin[physical_tile->index][from_physical_pin];

vpr/src/route/route_common.cpp

@@ -86,7 +86,8 @@ static t_trace_branch traceback_branch(int node, std::unordered_set<int>& main_b
 static std::pair<t_trace*, t_trace*> add_trace_non_configurable(t_trace* head, t_trace* tail, int node, std::unordered_set<int>& visited);
 static std::pair<t_trace*, t_trace*> add_trace_non_configurable_recurr(int node, std::unordered_set<int>& visited, int depth = 0);
 
-static vtr::vector<ClusterNetId, std::vector<int>> load_net_rr_terminals(const t_rr_node_indices& L_rr_node_indices);
+static vtr::vector<ClusterNetId, std::vector<int>> load_net_rr_terminals(const t_rr_node_indices& L_rr_node_indices,
+                                                                         std::unordered_map<int, ClusterBlockId>* rr_net_map);
 static vtr::vector<ClusterBlockId, std::vector<int>> load_rr_clb_sources(const t_rr_node_indices& L_rr_node_indices);
 
 static t_clb_opins_used alloc_and_load_clb_opins_used_locally();
@@ -479,7 +480,7 @@ void init_route_structs(int bb_factor) {
     Bucket::init(device_ctx.grid);
 
     //Various look-ups
-    route_ctx.net_rr_terminals = load_net_rr_terminals(device_ctx.rr_node_indices);
+    route_ctx.net_rr_terminals = load_net_rr_terminals(device_ctx.rr_node_indices, &route_ctx.rr_net_map);
     route_ctx.route_bb = load_route_bb(bb_factor);
     route_ctx.rr_blk_source = load_rr_clb_sources(device_ctx.rr_node_indices);
     route_ctx.clb_opins_used_locally = alloc_and_load_clb_opins_used_locally();
@@ -990,7 +991,11 @@ void reset_rr_node_route_structs() {
 /* Allocates and loads the route_ctx.net_rr_terminals data structure. For each net it stores the rr_node   *
  * index of the SOURCE of the net and all the SINKs of the net [clb_nlist.nets()][clb_nlist.net_pins()].    *
  * Entry [inet][pnum] stores the rr index corresponding to the SOURCE (opin) or SINK (ipin) of the pin.     */
-static vtr::vector<ClusterNetId, std::vector<int>> load_net_rr_terminals(const t_rr_node_indices& L_rr_node_indices) {
+static vtr::vector<ClusterNetId, std::vector<int>> load_net_rr_terminals(
+    const t_rr_node_indices& L_rr_node_indices,
+    std::unordered_map<int, ClusterBlockId>* rr_net_map) {
+    VTR_ASSERT(rr_net_map != nullptr);
+    rr_net_map->clear();
     vtr::vector<ClusterNetId, std::vector<int>> net_rr_terminals;
 
     auto& cluster_ctx = g_vpr_ctx.clustering();
@@ -1020,6 +1025,16 @@ static vtr::vector<ClusterNetId, std::vector<int>> load_net_rr_terminals(const t
             int inode = get_rr_node_index(L_rr_node_indices, i, j, (pin_count == 0 ? SOURCE : SINK), /* First pin is driver */
                                           iclass);
             net_rr_terminals[net_id][pin_count] = inode;
+
+            auto result = rr_net_map->insert(std::make_pair(inode, block_id));
+            // If the map already contains an entry for inode, make sure it
+            // is consistent with the existing entry.
+            if (!result.second && block_id != result.first->second) {
+                VPR_FATAL_ERROR(VPR_ERROR_ROUTE,
+                                "Clustered netlist has inconsistent rr node mapping, class rr node %d has two block ids %zu and %zu?",
+                                inode, (size_t)block_id, (size_t)result.first->second);
+            }
+
             pin_count++;
         }
     }
@@ -1263,11 +1278,18 @@ void print_route(FILE* fp, const vtr::vector<ClusterNetId, t_traceback>& traceba
                     fprintf(fp, "%d  ", device_ctx.rr_nodes[inode].ptc_num());
 
                     if (!is_io_type(device_ctx.grid[ilow][jlow].type) && (rr_type == IPIN || rr_type == OPIN)) {
+                        // Go from IPIN/OPIN to SOURCE/SINK
+                        auto* type = device_ctx.grid[ilow][jlow].type;
                         int pin_num = device_ctx.rr_nodes[inode].ptc_num();
-                        int xoffset = device_ctx.grid[ilow][jlow].width_offset;
-                        int yoffset = device_ctx.grid[ilow][jlow].height_offset;
-                        ClusterBlockId iblock = place_ctx.grid_blocks[ilow - xoffset][jlow - yoffset].blocks[0];
-                        VTR_ASSERT(iblock);
+                        int iclass = type->pin_class[pin_num];
+                        int class_inode = get_rr_node_index(device_ctx.rr_node_indices,
+                                                            ilow, jlow, (rr_type == OPIN ? SOURCE : SINK), iclass);
+
+                        // Use the rr_net_map to go from class inode back to ClusterBlockId.
+                        auto itr = route_ctx.rr_net_map.find(class_inode);
+                        VTR_ASSERT(itr != route_ctx.rr_net_map.end());
+                        ClusterBlockId iblock = itr->second;
+
                         t_pb_graph_pin* pb_pin = get_pb_graph_node_pin_from_block_pin(iblock, pin_num);
                         t_pb_type* pb_type = pb_pin->parent_node->pb_type;
                         fprintf(fp, " %s.%s[%d] ", pb_type->name, pb_pin->port->name, pb_pin->pin_number);