simulation mem leak - latch names array in create latch#996

jeanlego merged 3 commits intoverilog-to-routing:masterverilog-to-routing/vtr-verilog-to-routing:masterfrom

CAS-Atlantic:simulation_mem_leak_latch_namesCAS-Atlantic/vtr-verilog-to-routing:simulation_mem_leak_latch_namesCopy head branch name to clipboard