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simulation mem leak - latch names array in create latch #996

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sdamghan
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@sdamghan sdamghan commented Oct 9, 2019

How Has This Been Tested?

tested by make test odin

Types of changes

  • Bug fix (change which fixes an issue)
  • New feature (change which adds functionality)
  • Breaking change (fix or feature that would cause existing functionality to change)

Checklist:

  • My change requires a change to the documentation
  • I have updated the documentation accordingly
  • I have added tests to cover my changes
  • All new and existing tests passed

@probot-autolabeler probot-autolabeler bot added lang-cpp C/C++ code Odin Odin II Logic Synthesis Tool: Unsorted item labels Oct 9, 2019
Comment on lines 402 to 406
for (i = 0; i < input_token_count; i++)
// Except these two since they were assigned to new_node
if (i!=0 && i!=3)
vtr::free(names[i]);

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do strdup at line 371 and line 376 rather and here simply free them all
avoid complicated logic like this at all cost, change may occur in the code base and this would produce some unexpected side effect down the line

@sdamghan sdamghan force-pushed the simulation_mem_leak_latch_names branch from fb8c0b2 to 2e6dca1 Compare October 17, 2019 19:34
@@ -399,6 +399,10 @@ void create_latch_node_and_driver(FILE *file, Hashtable *output_nets_hash)
output_nets_hash->add(new_node->name, new_net);

/* Free the char** names */
for (i = 0; i < input_token_count; i++)
// Except these two since they were assigned to new_node
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remove that comment since it is not relevant anymore

@jeanlego jeanlego merged commit a97cada into verilog-to-routing:master Oct 18, 2019
@jeanlego jeanlego deleted the simulation_mem_leak_latch_names branch October 18, 2019 15:45
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2 participants