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Merged
merged 17 commits into from
Sep 17, 2019
Merged

Process XML tile tags #941

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3884a5e
initial addition of tile tag
acomodi Aug 27, 2019
a92e4f9
link physical/logical tiles with correct index
acomodi Aug 28, 2019
0302f45
update upgrade_arch.py script and added initial regression test
acomodi Aug 28, 2019
4d47606
run make format
acomodi Aug 28, 2019
2fb7d2d
fix port equivalence in physical tile ports
acomodi Sep 3, 2019
972b6e8
added updating architectures stage in .travis.yml
acomodi Sep 3, 2019
5ddc7df
fix valgrind memory leak
acomodi Sep 4, 2019
9823d18
moved pinloc calculation to read_xml_arch using physical tile info.
acomodi Sep 5, 2019
f64a957
run make format
acomodi Sep 5, 2019
27ce0d0
fixed memory leaks
acomodi Sep 6, 2019
1caeb45
remove equivalent tile regression test
acomodi Sep 6, 2019
eda5c91
addressed review comments
acomodi Sep 17, 2019
7d18a9a
Fixing pretty-print by removing blank spaces in XMLs
acomodi Sep 17, 2019
fb518ed
backed-out dev/upgrade_archs.sh CI script
acomodi Sep 17, 2019
8043c22
updated all test architecture files with pretty-print and tile tags
acomodi Sep 17, 2019
1fb36f1
Updated documentation to address the tiles tag addition
acomodi Sep 17, 2019
012116e
add port equivalence when checking ports of tiles and pb_types
acomodi Sep 17, 2019
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1 change: 1 addition & 0 deletions .travis.yml
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Original file line number Diff line number Diff line change
Expand Up @@ -39,6 +39,7 @@ addons:
- libxml++2.6-dev
- perl
- python
- python-lxml
- texinfo
- time
- valgrind
Expand Down
2 changes: 1 addition & 1 deletion dev/upgrade_vtr_archs.sh
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@@ -1,3 +1,3 @@
#!/bin/bash

find vpr libs/libarchfpga ODIN_II vtr_flow/arch -name '*.xml' | xargs -n 1 ./vtr_flow/scripts/upgrade_arch.py
find vpr libs/libarchfpga ODIN_II vtr_flow/arch utils/fasm/test -name '*.xml' | xargs -n 1 ./vtr_flow/scripts/upgrade_arch.py
130 changes: 84 additions & 46 deletions doc/src/arch/example_arch.xml
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@@ -1,10 +1,12 @@
<!-- VPR Architecture Specification File --><!-- Quick XML Primer:
<!-- VPR Architecture Specification File -->
<!-- Quick XML Primer:
* Data is hierarchical and composed of tags (similar to HTML)
* All tags must be of the form <foo>content</foo> OR <foo /> with the latter form indicating no content. Don't forget the slash at the end.
* Inside a start tag you may specify attributes in the form key="value". Refer to manual for the valid attributes for each element.
* Comments may be included anywhere in the document except inside a tag where it's attribute list is defined.
* Comments may contain any characters except two dashes.
--><!-- Architecture based off Stratix IV
-->
<!-- Architecture based off Stratix IV
Use closest ifar architecture: K06 N10 45nm fc 0.15 area-delay optimized, scale to 40 nm using linear scaling
n10k06l04.fc15.area1delay1.cmos45nm.bptm.cmos45nm.xml
* because documentation sparser for soft logic (delays not in QUIP), harder to track down, not worth our time considering the level of accuracy is approximate
Expand All @@ -21,7 +23,8 @@
created 4 18x18 mulitpliers, logiclocked them to a single DSP block, compile
result - 2 18x18 multipliers got packed together, the other 2 got ejected out of the logiclock region without error
conclusion - just take the 600 MHz as is, and Quartus II logiclock hasn't fixed the bug that I've seen it do to registers when I worked at Altera (ie. eject without warning)
--><architecture>
-->
<architecture>
<!-- ODIN II specific config -->
<models>
<model name="multiply">
Expand Down Expand Up @@ -74,23 +77,73 @@
</output_ports>
</model>
</models>
<tiles>
<tile name="io" capacity="8">
<equivalent_sites>
<site pb_type="io"/>
</equivalent_sites>
<input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/>
<clock name="clock" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<pinlocations pattern="custom">
<loc side="left">io.outpad io.inpad io.clock</loc>
<loc side="top">io.outpad io.inpad io.clock</loc>
<loc side="right">io.outpad io.inpad io.clock</loc>
<loc side="bottom">io.outpad io.inpad io.clock</loc>
</pinlocations>
</tile>
<tile name="clb">
<equivalent_sites>
<site pb_type="clb"/>
</equivalent_sites>
<input name="I" num_pins="33" equivalent="full"/>
<output name="O" num_pins="10" equivalent="instance"/>
<clock name="clk" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<pinlocations pattern="spread"/>
</tile>
<tile name="mult_36" height="4">
<equivalent_sites>
<site pb_type="mult_36"/>
</equivalent_sites>
<input name="a" num_pins="36"/>
<input name="b" num_pins="36"/>
<output name="out" num_pins="72"/>
<pinlocations pattern="spread"/>
</tile>
<tile name="memory" height="6">
<equivalent_sites>
<site pb_type="memory"/>
</equivalent_sites>
<input name="addr1" num_pins="17"/>
<input name="addr2" num_pins="17"/>
<input name="data" num_pins="72"/>
<input name="we1" num_pins="1"/>
<input name="we2" num_pins="1"/>
<output name="out" num_pins="72"/>
<clock name="clk" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<pinlocations pattern="spread"/>
</tile>
</tiles>
<!-- ODIN II specific config ends -->
<!-- Physical descriptions begin (area optimized for N8-K6-L4 -->
<layout>
<auto_layout aspect_ratio="1.0">
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
<perimeter type="io" priority="100"/>
<corners type="EMPTY" priority="101"/>
<!--Fill with 'clb'-->
<fill type="clb" priority="10"/>
<!--Column of 'mult_36' with 'EMPTY' blocks wherever a 'mult_36' does not fit. Vertical offset by 1 for perimeter.-->
<col type="mult_36" startx="4" starty="1" repeatx="8" priority="20"/>
<col type="EMPTY" startx="4" repeatx="8" starty="1" priority="19"/>
<!--Column of 'memory' with 'EMPTY' blocks wherever a 'memory' does not fit. Vertical offset by 1 for perimeter.-->
<col type="memory" startx="2" starty="1" repeatx="8" priority="20"/>
<col type="EMPTY" startx="2" repeatx="8" starty="1" priority="19"/>
</auto_layout>
</layout>
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
<perimeter type="io" priority="100"/>
<corners type="EMPTY" priority="101"/>
<!--Fill with 'clb'-->
<fill type="clb" priority="10"/>
<!--Column of 'mult_36' with 'EMPTY' blocks wherever a 'mult_36' does not fit. Vertical offset by 1 for perimeter.-->
<col type="mult_36" startx="4" starty="1" repeatx="8" priority="20"/>
<col type="EMPTY" startx="4" repeatx="8" starty="1" priority="19"/>
<!--Column of 'memory' with 'EMPTY' blocks wherever a 'memory' does not fit. Vertical offset by 1 for perimeter.-->
<col type="memory" startx="2" starty="1" repeatx="8" priority="20"/>
<col type="EMPTY" startx="2" repeatx="8" starty="1" priority="19"/>
</auto_layout>
</layout>
<device>
<sizing R_minW_nmos="6065.520020" R_minW_pmos="18138.500000"/>
<area grid_logic_tile_area="14813.392"/>
Expand All @@ -100,13 +153,13 @@
<y distr="uniform" peak="1.000000"/>
</chan_width_distr>
<switch_block type="wilton" fs="3"/>
<connection_block input_switch_name="ipin_cblock"/>
</device>
<connection_block input_switch_name="ipin_cblock"/>
</device>
<switchlist>
<switch type="mux" name="0" R="0.000000" Cin="0.000000e+00" Cout="0.000000e+00" Tdel="6.837e-11" mux_trans_size="2.630740" buf_size="27.645901"/>
<!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
<switch type="mux" name="ipin_cblock" R="1516.380005" Cout="0." Cin="0.000000e+00" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
</switchlist>
<!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
<switch type="mux" name="ipin_cblock" R="1516.380005" Cout="0." Cin="0.000000e+00" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
</switchlist>
<segmentlist>
<segment freq="1.000000" length="4" type="unidir" Rmetal="0.000000" Cmetal="0.000000e+00">
<mux name="0"/>
Expand All @@ -116,7 +169,7 @@
</segmentlist>
<complexblocklist>
<!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
<pb_type name="io" capacity="8">
<pb_type name="io">
<input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/>
<clock name="clock" num_pins="1"/>
Expand All @@ -141,22 +194,14 @@
</direct>
</interconnect>
</mode>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<!-- IOs go on the periphery of the FPGA, for consistency,
make it physically equivalent on all sides so that only one definition of I/Os is needed.
If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
-->
<pinlocations pattern="custom">
<loc side="left">io.outpad io.inpad io.clock</loc>
<loc side="top">io.outpad io.inpad io.clock</loc>
<loc side="right">io.outpad io.inpad io.clock</loc>
<loc side="bottom">io.outpad io.inpad io.clock</loc>
</pinlocations>
</pb_type>

</pb_type>
<pb_type name="clb">
<input name="I" num_pins="33" equivalent="full"/> <!-- NOTE: Logically Equivalent -->
<output name="O" num_pins="10" equivalent="instance"/> <!-- NOTE: Logically Equivalent -->
<input name="I" num_pins="33" equivalent="full"/><!-- NOTE: Logically Equivalent -->
<output name="O" num_pins="10" equivalent="instance"/><!-- NOTE: Logically Equivalent -->
<clock name="clk" num_pins="1"/>
<!-- Describe basic logic element -->
<pb_type name="ble" num_pb="10">
Expand Down Expand Up @@ -209,12 +254,9 @@
<complete name="clks" input="clb.clk" output="ble[9:0].clk"/>
<direct name="clbouts" input="ble[9:0].out" output="clb.O"/>
</interconnect>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<pinlocations pattern="spread"/>
</pb_type>

</pb_type>
<!-- This is the 36*36 uniform mult -->
<pb_type name="mult_36" height="4">
<pb_type name="mult_36">
<input name="a" num_pins="36"/>
<input name="b" num_pins="36"/>
<output name="out" num_pins="72"/>
Expand Down Expand Up @@ -304,11 +346,9 @@
</mode>
<fc_in type="frac">0.15</fc_in>
<fc_out type="frac">0.10</fc_out>
<pinlocations pattern="spread"/>
</pb_type>

</pb_type>
<!-- Memory based off Stratix IV 144K memory. Setup time set to match flip-flop setup time at 45 nm. Clock to q based off 144K max MHz -->
<pb_type name="memory" height="6">
<pb_type name="memory">
<input name="addr1" num_pins="17"/>
<input name="addr2" num_pins="17"/>
<input name="data" num_pins="72"/>
Expand Down Expand Up @@ -492,8 +532,6 @@
<direct name="clk" input="memory.clk" output="mem_18194x9_sp.clk"/>
</interconnect>
</mode>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<pinlocations pattern="spread"/>
</pb_type>
</pb_type>
</complexblocklist>
</architecture>
</architecture>
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