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verilog-to-routing / vtr-verilog-to-routing Public

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Process XML tile tags#941

Merged

kmurray merged 17 commits intoverilog-to-routing:masterverilog-to-routing/vtr-verilog-to-routing:masterfrom

acomodi:add-tile-tagsacomodi/vtr-verilog-to-routing:add-tile-tagsCopy head branch name to clipboard

Sep 17, 2019

Conversation Commits17 (17)Checks Files changed

Merged

Process XML tile tags#941
kmurray merged 17 commits intoverilog-to-routing:masterfrom
acomodi:add-tile-tags

Commits

Commits on Sep 17, 2019

initial addition of tile tag
acomodi
committed
link physical/logical tiles with correct index
acomodi
committed
update upgrade_arch.py script and added initial regression test
acomodi
committed
run make format
acomodi
committed
fix port equivalence in physical tile ports
acomodi
committed
added updating architectures stage in .travis.yml
acomodi
committed
fix valgrind memory leak
acomodi
committed
moved pinloc calculation to read_xml_arch using physical tile info.
acomodi
committed
run make format
acomodi
committed
fixed memory leaks
acomodi
committed
remove equivalent tile regression test
acomodi
committed
addressed review comments
acomodi
committed
Fixing pretty-print by removing blank spaces in XMLs
acomodi
committed
backed-out dev/upgrade_archs.sh CI script
acomodi
committed
updated all test architecture files with pretty-print and tile tags
acomodi
committed
Updated documentation to address the tiles tag addition
acomodi
committed
add port equivalence when checking ports of tiles and pb_types
acomodi
committed

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