Clock modeling 2

libs/libarchfpga/src/arch_util.cpp

@@ -145,15 +145,6 @@ void free_arch(t_arch* arch) {
     }
     delete[] arch->Switches;
     arch->Switches = nullptr;
-    for (int i = 0; i < arch->num_segments; ++i) {
-        vtr::free(arch->Segments[i].cb);
-        arch->Segments[i].cb = nullptr;
-        vtr::free(arch->Segments[i].sb);
-        arch->Segments[i].sb = nullptr;
-        vtr::free(arch->Segments[i].name);
-        arch->Segments[i].name = nullptr;
-    }
-    vtr::free(arch->Segments);
     t_model *model = arch->models;
     while (model) {
         t_model_ports *input_port = model->inputs;
@@ -265,7 +256,8 @@ void free_type_descriptors(t_type_descriptor* type_descriptors, int num_type_des
             vtr::free(type_descriptors[i].class_inf[j].pinlist);
         }
         vtr::free(type_descriptors[i].class_inf);
-        vtr::free(type_descriptors[i].is_global_pin);
+        vtr::free(type_descriptors[i].is_ignored_pin);
+        vtr::free(type_descriptors[i].is_pin_global);
         vtr::free(type_descriptors[i].pin_class);
 
         free_pb_type(type_descriptors[i].pb_type);
@@ -536,7 +528,7 @@ void SetupEmptyType(t_type_descriptor* cb_type_descriptors,
 	type->num_class = 0;
 	type->class_inf = nullptr;
 	type->pin_class = nullptr;
-	type->is_global_pin = nullptr;
+	type->is_ignored_pin = nullptr;
 	type->pb_type = nullptr;
 	type->area = UNDEFINED;
     type->switchblock_locations = vtr::Matrix<e_sb_type>({{size_t(type->width), size_t(type->height)}}, e_sb_type::FULL);
@@ -1346,10 +1338,10 @@ void primitives_annotation_clock_match(
 }
 
 
-t_segment_inf* find_segment(const t_arch* arch, std::string name) {
+const t_segment_inf* find_segment(const t_arch* arch, std::string name) {
 
-    for (int i = 0; i < arch->num_segments; ++i) {
-        t_segment_inf* seg = &arch->Segments[i];
+    for (size_t i = 0; i < (arch->Segments).size(); ++i) {
+        const t_segment_inf* seg = &arch->Segments[i];
         if (seg->name == name) {
             return seg;
         }

libs/libarchfpga/src/arch_util.h

@@ -73,7 +73,7 @@ void primitives_annotation_clock_match(
 		t_pin_to_pin_annotation *annotation, t_pb_type * parent_pb_type);
 
 bool segment_exists(const t_arch* arch, std::string name);
-t_segment_inf* find_segment(const t_arch* arch, std::string name);
+const t_segment_inf* find_segment(const t_arch* arch, std::string name);
 bool is_library_model(const char* model_name);
 bool is_library_model(const t_model* model);
 #endif

libs/libarchfpga/src/clock_types.h

@@ -0,0 +1,64 @@
+#ifndef CLOCK_TYPES_H
+#define CLOCK_TYPES_H
+
+#include <string>
+#include <vector>
+
+enum class e_clock_type {
+    SPINE,
+    RIB,
+    H_TREE
+};
+
+struct t_metal_layer {
+    float r_metal;
+    float c_metal;
+};
+
+struct t_wire_repeat {
+    std::string x;
+    std::string y;
+};
+
+struct t_wire {
+    std::string start;
+    std::string end;
+    std::string position;
+};
+
+struct t_clock_drive {
+    std::string name;
+    std::string offset;
+    int arch_switch_idx;
+};
+
+struct t_clock_taps {
+    std::string name;
+    std::string offset;
+    std::string increment;
+};
+
+struct t_clock_network_arch {
+    std::string name;
+    int num_inst;
+
+    e_clock_type type;
+
+    std::string metal_layer;
+    t_wire wire;
+    t_wire_repeat repeat;
+    t_clock_drive drive;
+    t_clock_taps tap;
+};
+
+struct t_clock_connection_arch {
+    std::string from;
+    std::string to;
+    int arch_switch_idx;
+    std::string locationx;
+    std::string locationy;
+    float fc;
+};
+
+#endif
+

libs/libarchfpga/src/echo_arch.cpp

@@ -87,7 +87,7 @@ void EchoArch(const char *EchoFile, const t_type_descriptor* Types,
                 VTR_ASSERT(false);
             }
             fprintf(Echo, " fc_value: %f", fc_spec.fc_value);
-            fprintf(Echo, " segment: %s", arch->Segments[fc_spec.seg_index].name);
+            fprintf(Echo, " segment: %s", arch->Segments[fc_spec.seg_index].name.c_str());
             fprintf(Echo, " pins:");
             for (int pin : fc_spec.pins) {
                 fprintf(Echo, " %d", pin);
@@ -249,7 +249,7 @@ void PrintArchInfo(FILE * Echo, const t_arch *arch) {
 	//Segment List
 	fprintf(Echo, "*************************************************\n");
 	fprintf(Echo, "Segment List:\n");
-	for (i = 0; i < arch->num_segments; i++) {
+	for (i = 0; i < (int)(arch->Segments).size(); i++) {
 		struct t_segment_inf seg = arch->Segments[i];
 		fprintf(Echo,
 				"\tSegment[%d]: frequency %d length %d R_metal %e C_metal %e\n",
@@ -267,7 +267,7 @@ void PrintArchInfo(FILE * Echo, const t_arch *arch) {
 		}
 
 		fprintf(Echo, "\t\t\t\tcb ");
-		for (j = 0; j < seg.cb_len; j++) {
+		for (j = 0; j < (int)seg.cb.size(); j++) {
 			if (seg.cb[j]) {
 				fprintf(Echo, "1 ");
 			} else {
@@ -277,7 +277,7 @@ void PrintArchInfo(FILE * Echo, const t_arch *arch) {
 		fprintf(Echo, "\n");
 
 		fprintf(Echo, "\t\t\t\tsb ");
-		for (j = 0; j < seg.sb_len; j++) {
+		for (j = 0; j < (int)seg.sb.size(); j++) {
 			if (seg.sb[j]) {
 				fprintf(Echo, "1 ");
 			} else {

libs/libarchfpga/src/physical_types.cpp

@@ -103,7 +103,7 @@ static e_directionality switch_type_directionaity(SwitchType type) {
  * t_type_descriptor
  */
 
-std::vector<int> t_type_descriptor::get_clock_pins_indices () {
+std::vector<int> t_type_descriptor::get_clock_pins_indices () const {
 
     VTR_ASSERT(this->pb_type); // assert not a nullptr
 

libs/libarchfpga/src/physical_types.h

@@ -28,13 +28,15 @@
 
 #include <functional>
 #include <vector>
+#include <unordered_map>
 #include <string>
 #include <map>
 #include <limits>
 
 #include "vtr_ndmatrix.h"
 
 #include "logic_types.h"
+#include "clock_types.h"
 
 //Forward declarations
 struct t_clock_arch;
@@ -434,7 +436,12 @@ constexpr int DEFAULT_SWITCH = -2;
  * pin_avg_width_offset: Average width offset to specified pin (exact if only a single physical pin instance)
  * pin_avg_height_offset: Average height offset to specified pin (exact if only a single physical pin instance)
  * pin_class: The class a pin belongs to
- * is_global_pin: Whether or not a pin is global (hence not routed)
+ * is_ignored_pin: Whether or not a pin is ignored durring rr_graph generation and routing.
+ *                 This is usually the case for clock pins and other global pins unless the
+ *                 clock_modeling option is set to route the clock through regular inter-block
+ *                 wiring or through a dedicated clock network.
+ * is_pin_global: Whether or not this pin is marked as global. Clock pins and other specified
+ *                global pins in the architecture file are marked as global.
  *
  * fc_specs: The Fc specifications for all pins
  *
@@ -475,7 +482,8 @@ struct t_type_descriptor /* TODO rename this.  maybe physical type descriptor or
     std::vector<int> pin_width_offset; //[0..num_pins-1]
     std::vector<int> pin_height_offset; //[0..num_pins-1]
 	int *pin_class = nullptr; /* [0..num_pins-1] */
-	bool *is_global_pin = nullptr; /* [0..num_pins-1] */
+	bool *is_ignored_pin = nullptr; /* [0..num_pins-1] */
+    bool *is_pin_global = nullptr; /* [0..num_pins -1] */
 
     std::vector<t_fc_specification> fc_specs;
 
@@ -495,7 +503,7 @@ struct t_type_descriptor /* TODO rename this.  maybe physical type descriptor or
 	int index = -1; /* index of type descriptor in array (allows for index referencing) */
 
     /* Returns the indices of pins that contain a clock for this physical logic block */
-    std::vector<int> get_clock_pins_indices();
+    std::vector<int> get_clock_pins_indices() const;
 
 };
 typedef const t_type_descriptor* t_type_ptr;
@@ -1006,7 +1014,7 @@ enum e_Fc_type {
  * (UDSD by AY) drivers: How do signals driving a routing track connect to   *
  *                       the track?                                          */
 struct t_segment_inf {
-	char *name;
+	std::string name;
 	int frequency;
 	int length;
 	short arch_wire_switch;
@@ -1017,10 +1025,8 @@ struct t_segment_inf {
 	float Rmetal;
 	float Cmetal;
 	enum e_directionality directionality;
-	bool *cb;
-	int cb_len;
-	bool *sb;
-	int sb_len;
+	std::vector<bool> cb;
+	std::vector<bool> sb;
 	//float Cmetal_per_m; /* Wire capacitance (per meter) */
 };
 
@@ -1260,6 +1266,12 @@ struct t_switchblock_inf{
 	std::vector<t_wireconn_inf> wireconns;	/* list of wire types/groups this SB will connect */
 };
 
+/* Clock related data types used for building a dedicated clock network */
+struct t_clock_arch_spec {
+    std::vector<t_clock_network_arch> clock_networks_arch;
+    std::unordered_map<std::string, t_metal_layer> clock_metal_layers;
+    std::vector<t_clock_connection_arch> clock_connections_arch;
+};
 
 /*   Detailed routing architecture */
 struct t_arch {
@@ -1272,9 +1284,8 @@ struct t_arch {
 	float R_minW_pmos;
 	int Fs;
 	float grid_logic_tile_area;
-	t_segment_inf * Segments;
-	int num_segments;
-	t_arch_switch_inf *Switches;
+	std::vector<t_segment_inf> Segments;
+    t_arch_switch_inf *Switches;
 	int num_switches;
 	t_direct_inf *Directs;
 	int num_directs;
@@ -1289,6 +1300,8 @@ struct t_arch {
     std::string ipin_cblock_switch_name;
 
     std::vector<t_grid_def> grid_layouts; //Set of potential device layouts
+
+    t_clock_arch_spec clock_arch; // Clock related data types
 };
 
 #endif