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Vpr viewer and flat routing on #3070

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@w0lek w0lek commented May 21, 2025

Related Issue

#3064

How Has This Been Tested?

manual test:

  • run vpr viewer with following command
    ./vpr test_post_verilog_arch.xml unconnected.eblif --device auto --timing_analysis on --constant_net_method route --clock_modeling ideal --exit_before_pack off --circuit_format eblif --absorb_buffer_luts off --route_chan_width 180 --flat_routing on --gen_post_synthesis_netlist on --timing_report_npaths 100 --timing_report_detail netlist --allow_dangling_combinational_nodes on --analysis --disp on
  • select different Node Id or Node name based on unconnected.route in search bar, observe visual.
    check that visual nodes representation corresponds to nodes listed in unconnected.route file.

Types of changes

  • Bug fix (change which fixes an issue)
  • New feature (change which adds functionality)
  • Breaking change (fix or feature that would cause existing functionality to change)

Checklist:

  • My change requires a change to the documentation
  • I have updated the documentation accordingly
  • I have added tests to cover my changes
  • All new and existing tests passed

@w0lek w0lek requested a review from amin1377 May 21, 2025 15:03
@w0lek w0lek marked this pull request as ready for review May 21, 2025 15:07
@github-actions github-actions bot added VPR VPR FPGA Placement & Routing Tool lang-cpp C/C++ code labels May 21, 2025
@w0lek w0lek marked this pull request as draft May 21, 2025 18:18
@w0lek w0lek marked this pull request as ready for review May 21, 2025 19:06
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