Update OpenFPGA Branch

.clang-format

@@ -15,7 +15,7 @@ AllowShortIfStatementsOnASingleLine: true
 AllowShortLoopsOnASingleLine: false
 AlwaysBreakAfterDefinitionReturnType: None
 AlwaysBreakAfterReturnType: None
-AlwaysBreakBeforeMultilineStrings: true
+AlwaysBreakBeforeMultilineStrings: false
 AlwaysBreakTemplateDeclarations: true
 BinPackArguments: true
 BinPackParameters: false
@@ -34,7 +34,7 @@ BraceWrapping:
   SplitEmptyFunction: false
   SplitEmptyRecord: true
   SplitEmptyNamespace: true
-BreakBeforeBinaryOperators: All
+BreakBeforeBinaryOperators: NonAssignment
 BreakBeforeBraces: Custom
 BreakBeforeInheritanceComma: false
 BreakBeforeTernaryOperators: true
@@ -68,10 +68,11 @@ IncludeIsMainRegex: '([-_](test|unittest))?$'
 IndentCaseLabels: true
 IndentWidth:     4
 IndentWrappedFunctionNames: false
-IndentPPDirectives: AfterHash
+IndentPPDirectives: None
+InsertNewlineAtEOF: true
 JavaScriptQuotes: Leave
 JavaScriptWrapImports: true
-KeepEmptyLinesAtTheStartOfBlocks: false
+KeepEmptyLinesAtTheStartOfBlocks: true
 MacroBlockBegin: ''
 MacroBlockEnd:   ''
 MaxEmptyLinesToKeep: 1

.github/scripts/hostsetup.sh

@@ -70,9 +70,8 @@ apt install -y \
   g++-9 \
   gcc-9 \
   wget \
-  openssl \
-  libssl-dev \
-  libtbb-dev
+  libtbb-dev \
+  openssl
 
 # installing the latest version of cmake
 apt install -y apt-transport-https ca-certificates gnupg

.github/scripts/install_dependencies.sh

@@ -55,9 +55,8 @@ sudo apt install -y \
   clang-16 \
   clang-17 \
   clang-18 \
-  clang-format-14 \
-  libtbb-dev \
-  openssl
+  clang-format-18 \
+  libtbb-dev
 
 pip install -r requirements.txt
 

.github/workflows/nightly_test.yml

@@ -22,8 +22,6 @@ on:
   #     - '**.md'
   #     - '**.rst'
   workflow_dispatch:
-  schedule:
-  - cron: '0 0 * * *' # daily
 
 # We want to cancel previous runs for a given PR or branch / ref if another CI
 # run is requested.
@@ -65,9 +63,9 @@ jobs:
           - {test: "vtr_reg_strong",             cores: "16", options: "",          cmake: "-DVTR_ASSERT_LEVEL=3",                                         extra_pkgs: "libeigen3-dev"}
           - {test: "vtr_reg_strong_odin",        cores: "16", options: "",          cmake: "-DVTR_ASSERT_LEVEL=3 -DWITH_ODIN=ON",                          extra_pkgs: "libeigen3-dev"}
           - {test: "vtr_reg_strong_odin",        cores: "16", options: "-skip_qor", cmake: "-DVTR_ASSERT_LEVEL=3 -DVTR_ENABLE_SANITIZE=ON -DWITH_ODIN=ON", extra_pkgs: "libeigen3-dev"}
-          # - {test: "vtr_reg_system_verilog",     cores: "16", options: "",          cmake: "-DYOSYS_F4PGA_PLUGINS=ON",                                     extra_pkgs: ""} # Test turned off -> F4PGA conflicts with Yosys (version 42)
+          - {test: "vtr_reg_system_verilog",     cores: "16", options: "",          cmake: "-DSYNLIG_SYSTEMVERILOG=ON",                                     extra_pkgs: ""} 
           - {test: "odin_reg_strong",            cores: "16", options: "",          cmake: "-DWITH_ODIN=ON",                                               extra_pkgs: ""}
-          - {test: "parmys_reg_strong",          cores: "16", options: "",          cmake: "-DYOSYS_F4PGA_PLUGINS=OFF",                                     extra_pkgs: ""}
+          - {test: "parmys_reg_strong",          cores: "16", options: "",          cmake: "-DSYNLIG_SYSTEMVERILOG=ON",                                     extra_pkgs: ""}
 
     env:
       DEBIAN_FRONTEND: "noninteractive"

.github/workflows/nightly_test_manual.yml

@@ -0,0 +1,106 @@
+name: NightlyTestManual
+
+# This workflow can only be dispatched.
+on:
+  workflow_dispatch:
+
+  # Automatically runs every Sunday 5 AM UTC.
+  # Results should be ready ~15 hours later (Sunday 8 PM UTC), on time for Monday mornings.
+  schedule:
+    - cron:  '0 5 * * 0'
+
+# We want to cancel previous runs for a given PR or branch / ref if another CI
+# run is requested.
+# See: https://docs.github.com/en/actions/using-jobs/using-concurrency
+concurrency:
+  group: ${{ github.workflow }}-${{ github.event.pull_request.number || github.ref }}
+  cancel-in-progress: true
+
+env:
+  # default compiler for all non-compatibility tests
+  MATRIX_EVAL: "CC=gcc-13 && CXX=g++-13"
+
+jobs:
+  Run-tests:
+    # Prevents from running on forks where no custom runners are available
+    if: ${{ github.repository_owner == 'verilog-to-routing' }}
+
+    name: 'Nightly Tests Manual Run'
+    # This workflow is expected to take around 19 hours. Giving it 24 hours
+    # before timing out.
+    timeout-minutes: 1440
+    runs-on: [self-hosted, Linux, X64, SAVI]
+
+    steps:
+    # Clean previous runs of this workflow.
+    - name: 'Cleanup build folder'
+      run: |
+        rm -rf ./* || true
+        rm -rf ./.??* || true
+
+    # Checkout the VTR repo.
+    - uses: actions/checkout@v4
+      with:
+        submodules: 'true'
+
+    # Get the extra benchmarks
+    - name: 'Get Extra Benchmarks'
+      run: |
+        make get_titan_benchmarks
+        make get_ispd_benchmarks
+        ./dev/upgrade_vtr_archs.sh
+        make get_symbiflow_benchmarks
+
+    # Build VTR using the default build options.
+    - name: 'Build VTR'
+      run: |
+        make -j12
+        make env
+        source .venv/bin/activate
+        pip install -r requirements.txt
+
+    # Run all of the nightly tests.
+    # TODO: We could expose more parallelism if we had one task list which ran
+    #       all of these.
+    - name: 'Run Nightly Test 1'
+      if: success() || failure()
+      run: |
+        source .venv/bin/activate
+        ./run_reg_test.py -j12 vtr_reg_nightly_test1
+
+    - name: 'Run Nightly Test 2'
+      if: success() || failure()
+      run: |
+        source .venv/bin/activate
+        ./run_reg_test.py -j12 vtr_reg_nightly_test2
+
+    - name: 'Run Nightly Test 3'
+      if: success() || failure()
+      run: |
+        source .venv/bin/activate
+        ./run_reg_test.py -j12 vtr_reg_nightly_test3
+
+
+    - name: 'Run Nightly Test 4'
+      if: success() || failure()
+      run: |
+        source .venv/bin/activate
+        ./run_reg_test.py -j12 vtr_reg_nightly_test4
+
+    - name: 'Run Nightly Test 5'
+      if: success() || failure()
+      run: |
+        source .venv/bin/activate
+        ./run_reg_test.py -j12 vtr_reg_nightly_test5
+
+    - name: 'Run Nightly Test 6'
+      if: success() || failure()
+      run: |
+        source .venv/bin/activate
+        ./run_reg_test.py -j12 vtr_reg_nightly_test6
+
+    - name: 'Run Nightly Test 7'
+      if: success() || failure()
+      run: |
+        source .venv/bin/activate
+        ./run_reg_test.py -j12 vtr_reg_nightly_test7

.github/workflows/test.yml

@@ -89,6 +89,8 @@ jobs:
       with:
         python-version: 3.10.10
     - uses: actions/checkout@v4
+      with:
+        submodules: 'true'
 
     - name: Install dependencies
       run: ./.github/scripts/install_dependencies.sh
@@ -439,7 +441,6 @@ jobs:
         - { name: 'GCC 11 (Ubuntu Noble - 24.04)',    eval: 'CC=gcc-11 && CXX=g++-11',           }
         - { name: 'GCC 12 (Ubuntu Noble - 24.04)',    eval: 'CC=gcc-12 && CXX=g++-12',         }
         - { name: 'GCC 14 (Ubuntu Noble - 24.04)',    eval: 'CC=gcc-14 && CXX=g++-14',         }
-        - { name: 'Clang 15 (Ubuntu Noble - 24.04)',  eval: 'CC=clang-15 && CXX=clang++-15',   }
         - { name: 'Clang 16 (Ubuntu Noble - 24.04)',  eval: 'CC=clang-16 && CXX=clang++-16',   }
         - { name: 'Clang 17 (Ubuntu Noble - 24.04)',  eval: 'CC=clang-17 && CXX=clang++-17',   }
         - { name: 'Clang 18 (Ubuntu Noble - 24.04)',  eval: 'CC=clang-18 && CXX=clang++-18',   }

.gitmodules

@@ -1,6 +1,8 @@
 [submodule "libs/EXTERNAL/libcatch2"]
 	path = libs/EXTERNAL/libcatch2
 	url = https://github.com/catchorg/Catch2.git
+
+# fork where in branch v1.0.0_no_complication_warnings there are compilation warnings fixes for upstream tag v1.0.0 of sockpp
 [submodule "libs/EXTERNAL/sockpp"]
 	path = libs/EXTERNAL/sockpp
-	url = https://github.com/w0lek/sockpp.git # fork where in branch v1.0.0_no_complication_warnings there are compilation warnings fixes for upstream tag v1.0.0 of sockpp
+	url = https://github.com/w0lek/sockpp.git

.gitpod.Dockerfile

@@ -30,6 +30,7 @@ RUN apt-get update \
   python-lxml \
   qt5-default \
   wget \
+  default-jre \
   && apt-get clean \
   && rm -rf /var/lib/apt/lists/*
 

CHANGELOG.md

@@ -47,6 +47,64 @@ _The following are changes which have been implemented in the VTR master branch
 
 ### Removed
 
+
+## v9.0.0 - 2024-12-23
+
+### Added
+  * Support for Advanced Architectures:
+    * 3D FPGA and RAD architectures.
+    * Architectures with hard Networks-on-Chip (NoCs).
+    * Distinct horizontal and vertical channel widths and types.
+    * Diagonal routing wires and other complex wire shapes (L-shaped, T-shaped, ....).
+
+  * New Benchmark Suites:
+    * Koios: A deep-learning-focused benchmark suite with various design sizes.
+    * Hermes: Benchmarks utilizing hard NoCs.
+    * TitanNew: Large benchmarks targeting the Stratix 10 architecture.
+
+  * Commercial FPGAs Architecture Captures:
+    * Intel’s Stratix 10 FPGA architecture.
+    * AMD’s 7-series FPGA architecture.
+
+  * Parmys Logic Synthesis Flow:
+    * Better Verilog language coverage
+    * More efficient hard block mapping
+
+  * VPR Graphics Visualizations:
+    * New interface for improved usability and underlying graphics rewritten using EZGL/GTK to allow more UI widgets.
+    * Algorithm breakpoint visualizations for placement and routing algorithm debugging.
+    * User-guided (manual) placement optimization features.
+    * Enabled a live connection for client graphical application to VTR engines through sockets (server mode).
+    * Interactive timing path analysis (IPA) client using server mode.
+
+  * Performance Enhancements:
+    * Parallel router for faster inter-cluster routing or flat routing.
+
+  * Re-clustering API to modify packing decisions during the flow.
+  * Support for floorplanning and placement constraints.
+  * Unified intra- and inter-cluster (flat) routing.
+  * Comprehensive web-based VTR utilities and API documentation.
+
+### Changed
+  * The default values of many command line options (e.g. inner_num is 0.5 instead of 1.0)
+  * Changes to placement engine
+    * Smart centroid initial placement algorithm.
+    * Multiple smart placement directed moves.
+    * Reinforcement learning-based placement algorithm.
+  * Changes to routing engine
+    * Faster lookahead creation.
+    * More accurate lookahead for large blocks.
+    * More efficient heap and pruning strategies.
+    * max `pres_fac` capped to avoid possible numeric issues.
+
+
+### Fixed
+  * Many algorithmic and coding bugs are fixed in this release
+
+### Removed
+  * Breadth-first (non-timing-driven) router.
+  * Non-linear congestion placement cost.
+
 ## v8.0.0 - 2020-03-24
 
 ### Added

CMakeLists.txt

@@ -31,7 +31,6 @@ option(VTR_ENABLE_SANITIZE "Enable address/leak/undefined-behaviour sanitizers (
 option(VTR_ENABLE_PROFILING "Enable performance profiler (gprof)" OFF)
 option(VTR_ENABLE_COVERAGE "Enable code coverage tracking (gcov)" OFF)
 option(VTR_ENABLE_DEBUG_LOGGING "Enable debug logging" OFF)
-option(VTR_ENABLE_VERSION "Enable version number up-to-date during compilation" ON) 
 option(VTR_ENABLE_VERBOSE "Enable increased debug verbosity" OFF)
 option(SPEC_CPU "Enable SPEC CPU v8 support" OFF)
 
@@ -61,10 +60,10 @@ option(ODIN_SANITIZE "Enable building odin with sanitize flags" OFF)
 
 # Allow the user to enable building Yosys
 option(WITH_PARMYS "Enable Yosys as elaborator and parmys-plugin as partial mapper" ON)
-option(YOSYS_F4PGA_PLUGINS "Enable building and installing Yosys SystemVerilog and UHDM plugins" OFF)
+option(SYNLIG_SYSTEMVERILOG "Enable building and installing Synlig SystemVerilog and UHDM plugins" OFF)
 
-set(VTR_VERSION_MAJOR 8)
-set(VTR_VERSION_MINOR 1)
+set(VTR_VERSION_MAJOR 9)
+set(VTR_VERSION_MINOR 0)
 set(VTR_VERSION_PATCH 0)
 set(VTR_VERSION_PRERELEASE "dev")
 
@@ -94,9 +93,9 @@ add_definitions("-DVTR_ASSERT_LEVEL=${VTR_ASSERT_LEVEL}")
 include(CheckCXXCompilerFlag)
 
 #
-# We require c++17 support
+# We require c++20 support
 #
-set(CMAKE_CXX_STANDARD 17)
+set(CMAKE_CXX_STANDARD 20)
 set(CMAKE_CXX_STANDARD_REQUIRED ON)
 set(CMAKE_CXX_EXTENSIONS OFF) #No compiler specific extensions
 
@@ -161,7 +160,7 @@ else()
         "-Wcast-align"                  #Warn if a cast causes memory alignment changes
         "-Wshadow"                      #Warn if local variable shadows another variable
         "-Wformat=2"                    #Sanity checks for printf-like formatting
-        "-Wno-format-nonliteral"        # But don't worry about non-literal formtting (i.e. run-time printf format strings)
+        "-Wno-format-nonliteral"        # But don't worry about non-literal formatting (i.e. run-time printf format strings)
         "-Wlogical-op"                  #Checks for logical op when bit-wise expected
         "-Wmissing-declarations"        #Warn if a global function is defined with no declaration
         "-Wmissing-include-dirs"        #Warn if a user include directory is missing
@@ -179,10 +178,10 @@ else()
         "-Wduplicated-cond"             #Warn about identical conditions in if-else chains
         "-Wduplicated-branches"         #Warn when different branches of an if-else chain are equivalent
         "-Wnull-dereference"            #Warn about null pointer dereference execution paths
-        "-Wuninitialized"               #Warn about unitialized values
+        "-Wuninitialized"               #Warn about uninitialized values
         "-Winit-self"                   #Warn about self-initialization
         "-Wcatch-value=3"               #Warn when catch statements don't catch by reference
-        "-Wextra-semi"                  #Warn about redudnant semicolons
+        "-Wextra-semi"                  #Warn about redundant semicolons
         "-Wimplicit-fallthrough=3"      #Warn about case fallthroughs, but allow 'fallthrough' comments to suppress warnings
         #GCC-like optional
         #"-Wsuggest-final-types"         #Suggest where 'final' would help if specified on a type methods
@@ -454,7 +453,7 @@ if(${WITH_ODIN})
 endif()
 
 # handle cmake params to compile Yosys SystemVerilog/UHDM plugins
-if(${YOSYS_F4PGA_PLUGINS})
+if(${SYNLIG_SYSTEMVERILOG})
     # avoid compiling plugins in case the Parmys frontend is not active
     if(NOT ${WITH_PARMYS})
         message(SEND_ERROR "Utilizing SystemVerilog/UHDM plugins requires activating Parmys frontend. Please set WITH_PARMYS.")

Dockerfile

@@ -15,6 +15,7 @@ RUN apt-get update -qq \
     && apt-get -y install --no-install-recommends \
     wget \
     ninja-build \
+    default-jre \
     libeigen3-dev \
     libtbb-dev \
     python3-pip \