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Update OpenFPGA Branch #2979

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@amin1377 amin1377 commented Apr 14, 2025 •
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Update OpenFPGA with latest changes on VTR master branch

tangxifan and others added 30 commits April 12, 2025 15:03
@tangxifan @amin1377
[vpr] add missing support on tileable routing
cd1dff4
@tangxifan @amin1377
[vpr] now use the switch index from direct defintion
997a72a
@tangxifan @amin1377
[test] remove out-of-date koios entry
632f7aa
@tangxifan @amin1377
[vpr] syntax and sanity checks
0559025
@tangxifan @amin1377
[lib] support multiple ptc number for rr graph I/O
1350d55
@tangxifan @amin1377
[lib] update rr graph I/O auto-gen files
727fbeb
@tangxifan @amin1377
[lib] update rr graph reader
f2b1016
@tangxifan @amin1377
[lib] fixed a few bugs
e86c882
@tangxifan @amin1377
[vpr] fixed a bug where rr graph I/O always require node_ptc_nums
feea6d1
@tangxifan @amin1377
[vpr] debugging
922fed0
@tangxifan @amin1377
[lib] debugging
d03db90
@tangxifan @amin1377
[lib] fixed the bug in I/O of rrgraph. Seems that the ostream require…
b1d03c6 
… std:string after to_string conversion
@tangxifan @amin1377
[lib] add resize for ptc nums
e5a4fa4
@tangxifan @amin1377
[lib] fixed the bug on rr graph io. Should use temp_string_
5be9125
@tangxifan @amin1377
[lib] fixed a bug on node lookup assignment in RR graph I/O when supp…
15a6a7f 
…orting multiple ptc
@tangxifan @amin1377
[lib] now add rc data for CHANX and CHANY nodes in tileable rr graph
fa18ce0
@tangxifan @amin1377
[test] now use L1 and L4 in the tileable arch
fbc7797
@tangxifan @amin1377
[test] add new testcases for tileable rr graph
1606e98
@tangxifan @amin1377
[core] fixed a bug where Y-axis segments may not be found
e133c58
@tangxifan @amin1377
[core] add methods to identify opins for connection blocks
59cec73
@tangxifan @amin1377
[core] syntax
aae47fb
@tangxifan @amin1377
[core] fixed a bug on rr gsb when sorting edges from OPINs
cde781f
@tangxifan @amin1377
[core] add more debuggin messages
0e723b6
@Wang-Yuanqi-source @amin1377
Update device_grid_annotation.cpp
a497068
@Wang-Yuanqi-source @amin1377
Update tileable_chan_details_builder.cpp
0d940c0 
Add bend wires
@Wang-Yuanqi-source @amin1377
Update tileable_rr_graph_node_builder.cpp
e05a3dd
@Wang-Yuanqi-source @amin1377
Update tileable_rr_graph_gsb.h
65889cc
@Wang-Yuanqi-source @amin1377
Update tileable_rr_graph_edge_builder.cpp
2d7d141
@Wang-Yuanqi-source @amin1377
Update tileable_rr_graph_gsb.cpp
164566a
@Wang-Yuanqi-source @amin1377
Update tileable_rr_graph_gsb.h
3bf7656
@github-actions github-actions bot added VPR VPR FPGA Placement & Routing Tool Odin Odin II Logic Synthesis Tool: Unsorted item libarchfpga Library for handling FPGA Architecture descriptions docs Documentation lang-cpp C/C++ code infra Project Infrastructure build Build system scripts Utility & Infrastructure scripts lang-python Python code lang-make CMake/Make code lang-hdl Hardware Description Language (Verilog/VHDL) lang-shell Shell scripts (bash etc.) libvtrutil external_libs lang-netlist liblog libpugiutil Parmys labels Apr 14, 2025
@amin1377 amin1377 changed the title [WIP] Update OpenFPGA Branch Update OpenFPGA Branch Apr 15, 2025
@amin1377 amin1377 closed this Apr 16, 2025
@amin1377 amin1377 deleted the openfpga_update branch April 16, 2025 14:47
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build Build system docs Documentation external_libs infra Project Infrastructure lang-cpp C/C++ code lang-hdl Hardware Description Language (Verilog/VHDL) lang-make CMake/Make code lang-netlist lang-python Python code lang-shell Shell scripts (bash etc.) libarchfpga Library for handling FPGA Architecture descriptions liblog libpugiutil libvtrutil Odin Odin II Logic Synthesis Tool: Unsorted item Parmys scripts Utility & Infrastructure scripts VPR VPR FPGA Placement & Routing Tool
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@amin1377 @tangxifan @Wang-Yuanqi-source @Tulong4Dev @behzadmehmood @NadeemYaseen