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[AP] Fixed Small Bug in Solver and Placer #2928

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Merged
merged 1 commit into from
Mar 13, 2025
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[AP] Fixed Small Bug in Solver and Placer #2928

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4 changes: 1 addition & 3 deletions vpr/src/analytical_place/analytical_solver.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -169,13 +169,11 @@ void QPHybridSolver::init_linear_system() {
std::vector<Eigen::Triplet<double>> tripletList;
// Reserve enough space for the triplets. This is just to help with
// performance.
// This is an over-estimate that assumes that each net connnects to all
// moveable blocks using a star node.
// TODO: This can be made more space-efficient by getting the average fanout
// of all nets in the APNetlist. Ideally this should be not enough
// space, but be within a constant factor.
size_t num_nets = netlist_.nets().size();
tripletList.reserve(num_moveable_blocks_ * num_nets);
tripletList.reserve(num_nets);

// Create the connections using a hybrid connection model of the star and
// clique connnection models.
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37 changes: 30 additions & 7 deletions vpr/src/place/initial_placement.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -609,15 +609,38 @@ static bool try_centroid_placement(const t_pl_macro& pl_macro,
// If a flat placement is provided, use the flat placement to get the
// centroid.
find_centroid_loc_from_flat_placement(pl_macro, centroid_loc, flat_placement_info);
// If a centroid could not be found, or if the tile is not legal
// fall-back on the centroid of the neighbor blocks of this block.
// TODO: This may be more disruptive than needed for flat placement
// reconstruction. Ideally, we would search for a new tile
// location near the flat placement centroid.
if (!is_loc_on_chip({centroid_loc.x, centroid_loc.y, centroid_loc.layer}) ||
!is_loc_legal(centroid_loc, pr, block_type)) {
unplaced_blocks_to_update_their_score = find_centroid_loc(pl_macro, centroid_loc, blk_loc_registry);
found_legal_subtile = find_subtile_in_location(centroid_loc, block_type, blk_loc_registry, pr, rng);
// If the centroid is not legal, check for a neighboring block we
// can use instead.
bool neighbor_legal_loc = find_centroid_neighbor(centroid_loc,
block_type,
false,
blk_loc_registry,
rng);
if (!neighbor_legal_loc) {
// If we cannot find a neighboring block, fall back on the
// original find_centroid_loc function.
unplaced_blocks_to_update_their_score = find_centroid_loc(pl_macro, centroid_loc, blk_loc_registry);
found_legal_subtile = find_subtile_in_location(centroid_loc, block_type, blk_loc_registry, pr, rng);
} else {
found_legal_subtile = true;
}
} else {
// If this is a legal location for this block, check if any other
// blocks are at this subtile location.
const GridBlock& grid_blocks = blk_loc_registry.grid_blocks();
if (grid_blocks.block_at_location(centroid_loc)) {
// If there is a block at this subtile, try to find another
// subtile at this location to be placed in.
found_legal_subtile = find_subtile_in_location(centroid_loc,
block_type,
blk_loc_registry,
pr,
rng);
} else {
found_legal_subtile = true;
}
}
}

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8 changes: 4 additions & 4 deletions vtr_flow/tasks/regression_tests/vtr_reg_strong/basic_ap/config/golden_results.txt
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Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time
fixed_k6_frac_N8_22nm.xml single_wire.v common 1.44 vpr 75.50 MiB -1 -1 0.06 20472 1 0.01 -1 -1 33044 -1 -1 0 1 0 0 success v8.0.0-12213-gab28a6e25-dirty release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-03-02T13:12:27 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77316 1 1 0 2 0 1 2 17 17 289 -1 unnamed_device -1 -1 2 3 0 0 3 75.5 MiB 0.54 0.00 0.2714 -0.2714 -0.2714 nan 0.42 7.631e-06 4.788e-06 5.8704e-05 4.0805e-05 75.5 MiB 0.54 75.5 MiB 0.54 8 18 1 6.79088e+06 0 166176. 575.005 0.14 0.000842308 0.000774609 20206 45088 -1 18 1 1 1 114 40 0.7726 nan -0.7726 -0.7726 0 0 202963. 702.294 0.01 0.00 0.04 -1 -1 0.01 0.00078696 0.000736601
fixed_k6_frac_N8_22nm.xml single_ff.v common 1.60 vpr 75.69 MiB -1 -1 0.07 20716 1 0.02 -1 -1 33068 -1 -1 1 2 0 0 success v8.0.0-12213-gab28a6e25-dirty release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-03-02T13:12:27 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77508 2 1 3 3 1 3 4 17 17 289 -1 unnamed_device -1 -1 22 9 3 4 2 75.7 MiB 0.52 0.00 0.74674 -1.4524 -0.74674 0.74674 0.40 1.3477e-05 8.826e-06 8.6874e-05 6.3274e-05 75.7 MiB 0.52 75.7 MiB 0.52 20 27 1 6.79088e+06 13472 414966. 1435.87 0.24 0.000930532 0.000852446 22510 95286 -1 30 1 2 2 163 35 0.74674 0.74674 -1.43836 -0.74674 0 0 503264. 1741.40 0.03 0.00 0.08 -1 -1 0.03 0.00102904 0.00095538
fixed_k6_frac_N8_22nm.xml ch_intrinsics.v common 3.50 vpr 76.36 MiB -1 -1 0.24 22124 3 0.07 -1 -1 36540 -1 -1 61 99 1 0 success v8.0.0-12213-gab28a6e25-dirty release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-03-02T13:12:27 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78188 99 130 240 229 1 226 291 17 17 289 -1 unnamed_device -1 -1 838 18607 1985 1801 14821 76.4 MiB 0.69 0.00 1.6707 -127.089 -1.6707 1.6707 0.40 0.000610649 0.000537736 0.0140862 0.0125271 76.4 MiB 0.69 76.4 MiB 0.67 34 1822 16 6.79088e+06 1.36979e+06 618332. 2139.56 1.43 0.168901 0.149844 25102 150614 -1 1682 13 569 976 59358 18627 2.0466 2.0466 -143.074 -2.0466 -0.04337 -0.04337 787024. 2723.27 0.04 0.03 0.13 -1 -1 0.04 0.0351297 0.0316135
fixed_k6_frac_N8_22nm.xml diffeq1.v common 8.53 vpr 79.32 MiB -1 -1 0.37 26988 15 0.31 -1 -1 37340 -1 -1 47 162 0 5 success v8.0.0-12213-gab28a6e25-dirty release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-03-02T13:12:27 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 81220 162 96 817 258 1 719 310 17 17 289 -1 unnamed_device -1 -1 6797 28606 496 8327 19783 79.3 MiB 1.10 0.01 21.005 -1600.44 -21.005 21.005 0.39 0.0020065 0.00179053 0.066982 0.0598287 79.3 MiB 1.10 79.3 MiB 1.03 58 14305 35 6.79088e+06 2.61318e+06 997811. 3452.63 4.70 0.808118 0.727985 29710 251250 -1 12039 17 3605 8667 1087317 276398 20.4866 20.4866 -1547.03 -20.4866 0 0 1.25153e+06 4330.55 0.06 0.27 0.24 -1 -1 0.06 0.158734 0.14406
fixed_k6_frac_N8_22nm.xml single_wire.v common 1.44 vpr 75.95 MiB -1 -1 0.07 20456 1 0.01 -1 -1 33044 -1 -1 0 1 0 0 success v8.0.0-12241-g26615cb38 release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-03-12T19:05:19 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77772 1 1 0 2 0 1 2 17 17 289 -1 unnamed_device -1 -1 2 3 0 0 3 75.9 MiB 0.53 0.00 0.2714 -0.2714 -0.2714 nan 0.40 8.144e-06 5.14e-06 6.5759e-05 4.5693e-05 75.9 MiB 0.53 75.9 MiB 0.12 8 4 1 6.79088e+06 0 166176. 575.005 0.14 0.000860822 0.000793719 20206 45088 -1 14 1 1 1 125 46 0.7726 nan -0.7726 -0.7726 0 0 202963. 702.294 0.01 0.00 0.04 -1 -1 0.01 0.000788962 0.000735535
fixed_k6_frac_N8_22nm.xml single_ff.v common 1.62 vpr 75.58 MiB -1 -1 0.06 20712 1 0.02 -1 -1 33160 -1 -1 1 2 0 0 success v8.0.0-12241-g26615cb38 release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-03-12T19:05:19 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77392 2 1 3 3 1 3 4 17 17 289 -1 unnamed_device -1 -1 22 9 3 1 5 75.6 MiB 0.54 0.00 0.74674 -1.4524 -0.74674 0.74674 0.42 1.404e-05 9.436e-06 9.1283e-05 6.5781e-05 75.6 MiB 0.54 75.6 MiB 0.12 20 27 1 6.79088e+06 13472 414966. 1435.87 0.25 0.000949046 0.00086885 22510 95286 -1 26 1 2 2 102 24 0.691615 0.691615 -1.31306 -0.691615 0 0 503264. 1741.40 0.03 0.00 0.08 -1 -1 0.03 0.000851109 0.000786812
fixed_k6_frac_N8_22nm.xml ch_intrinsics.v common 2.89 vpr 76.61 MiB -1 -1 0.25 22244 3 0.07 -1 -1 36672 -1 -1 61 99 1 0 success v8.0.0-12241-g26615cb38 release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-03-12T19:05:19 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78444 99 130 240 229 1 226 291 17 17 289 -1 unnamed_device -1 -1 836 23427 2473 2563 18391 76.6 MiB 0.70 0.00 1.6707 -124.826 -1.6707 1.6707 0.40 0.00061736 0.000542944 0.0172452 0.0152919 76.6 MiB 0.70 76.6 MiB 0.22 34 1887 16 6.79088e+06 1.36979e+06 618332. 2139.56 0.79 0.150985 0.133999 25102 150614 -1 1720 15 582 1038 63837 19910 2.0466 2.0466 -148.606 -2.0466 -0.0867399 -0.04337 787024. 2723.27 0.04 0.04 0.13 -1 -1 0.04 0.0399279 0.0357637
fixed_k6_frac_N8_22nm.xml diffeq1.v common 9.15 vpr 78.08 MiB -1 -1 0.36 27240 15 0.31 -1 -1 37212 -1 -1 47 162 0 5 success v8.0.0-12241-g26615cb38 release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-03-12T19:05:19 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 79952 162 96 817 258 1 719 310 17 17 289 -1 unnamed_device -1 -1 6924 26510 456 7435 18619 78.1 MiB 1.11 0.01 21.2724 -1567 -21.2724 21.2724 0.41 0.00221014 0.00195675 0.0629161 0.055951 78.1 MiB 1.11 78.1 MiB 0.37 60 13918 24 6.79088e+06 2.61318e+06 1.01997e+06 3529.29 5.33 0.777791 0.697039 29998 257685 -1 11776 17 3478 8557 1021735 259483 20.9878 20.9878 -1554.55 -20.9878 0 0 1.27783e+06 4421.56 0.06 0.25 0.25 -1 -1 0.06 0.153701 0.139186
8 changes: 4 additions & 4 deletions ...ow/tasks/regression_tests/vtr_reg_strong/strong_ap/none_detailed_placer/config/config.txt
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Expand Up @@ -18,27 +18,27 @@ arch_list_add=k6_frac_N10_40nm.xml
# Add circuits to list to sweep
circuit_list_add=apex4.pre-vpr.blif
circuit_list_add=des.pre-vpr.blif
circuit_list_add=ex1010.pre-vpr.blif
circuit_list_add=seq.pre-vpr.blif
# circuit_list_add=ex1010.pre-vpr.blif

# Constrain the circuits to their devices
circuit_constraint_list_add=(apex4.pre-vpr.blif, device=mcnc_medium)
circuit_constraint_list_add=(seq.pre-vpr.blif, device=mcnc_medium)
circuit_constraint_list_add=(des.pre-vpr.blif, device=mcnc_large)
circuit_constraint_list_add=(ex1010.pre-vpr.blif, device=mcnc_large)
# circuit_constraint_list_add=(ex1010.pre-vpr.blif, device=mcnc_large)

# Constrain the IOs
circuit_constraint_list_add=(apex4.pre-vpr.blif, constraints=../../../../../mcnc/constraints/apex4_io_constraint.xml)
circuit_constraint_list_add=(seq.pre-vpr.blif, constraints=../../../../../mcnc/constraints/seq_io_constraint.xml)
circuit_constraint_list_add=(des.pre-vpr.blif, constraints=../../../../../mcnc/constraints/des_io_constraint.xml)
circuit_constraint_list_add=(ex1010.pre-vpr.blif, constraints=../../../../../mcnc/constraints/ex1010_io_constraint.xml)
# circuit_constraint_list_add=(ex1010.pre-vpr.blif, constraints=../../../../../mcnc/constraints/ex1010_io_constraint.xml)

# Constrain the circuits to their channel widths
# 1.3 * minW
circuit_constraint_list_add=(apex4.pre-vpr.blif, route_chan_width=78)
circuit_constraint_list_add=(seq.pre-vpr.blif, route_chan_width=78)
circuit_constraint_list_add=(des.pre-vpr.blif, route_chan_width=44)
circuit_constraint_list_add=(ex1010.pre-vpr.blif, route_chan_width=114)
# circuit_constraint_list_add=(ex1010.pre-vpr.blif, route_chan_width=114)

# Parse info and how to parse
parse_file=vpr_fixed_chan_width.txt
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