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Add 3D Architectures #2444
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1e166b3
create a readme file for 3d arch dir
amin1377 04e1370
create separate directoris for 3d architecture
amin1377 10b5c89
write a readme for 3d architectures
amin1377 9531fe7
remove all 3d koios archs
amin1377 075488e
add the new 3d koios archs
amin1377 66f645b
set auto layout for two koios benchmark
amin1377 a1bedef
remove 3d koios with different sizes and put all of them in a single …
amin1377 fda7a69
update the readme file based on new koios arch files
amin1377 8e73bc6
change the name of the inter-layer cblock sw
amin1377 75d775d
add delay to 3d siv mech
amin1377 6ba7ffc
add inter-layer delay to 3d siv arch 10x10 noc
amin1377 7433398
fix the naming of 3d SIV archs
amin1377 855f061
update readme on 3d siv files - update 3d simple arch
amin1377 da6c552
update readme on 3d simple arch
amin1377 3a3a3c0
update config files with the new dir of 3d arch
amin1377 8b57a03
add a new test for 3d siv
amin1377 3c039fc
add golden results for 3d SIV
amin1377 7533449
clarify some statements in 3d arch readme file
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| # 3D FPGA Architectures | ||
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| This directory contains architecture files for 3D FPGAs. The architectures are divided into three sub-directories: | ||
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| 1. **koios_3d:** | ||
| - Contains architecture files based on the [k6FracN10LB_mem20K_complexDSP_customSB_22nm](../COFFE_22nm/k6FracN10LB_mem20K_complexDSP_customSB_22nm.clustered.xml) architecture, utilized in Koios benchmarks. | ||
| - Inside the architecture file, the fabric with multiple sizes based on the sector size is defined. | ||
| - Routing resource and switch delays in this architecture are configured for 7 nm technology, with a delay of 73 ps. | ||
| - Detailed information on how these delays are obtained can be found in the paper "Into the Third Dimension: Architecture Exploration Tools for 3D Reconfigurable Acceleration Devices," presented at FPT '23. | ||
| - **Architectures:** | ||
| - `3d_full_OPIN_inter_die_k6FracN10LB_mem20k_complexDSP_customSB_7nm.xml` | ||
| - The inter-die connection is only from output pins, with all output pins connected to the channel on the same die and the other. | ||
| - Inside the architecture file, the fabric with multiple sizes based on the sector size is defined. | ||
| - `3d_limited_OPIN_inter_die_k6FracN10LB_mem20k_complexDSP_customSB_7nm.xml` | ||
| - The inter-die connection is only from output pins, with all OPINs of BRAMs and DSPs connected to the channels on the same die and the other die. | ||
| - Only 60% of the OPINs of CLBs are connected to the channels on the other die and all of them can get connected to the channels on the same die. | ||
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| 2. **stratixiv_3d:** | ||
| - Contains architecture files based on a [StratixIV-like](../titan/stratixiv_arch.timing.xml) architecture. | ||
| - Delays of switches and routing resources are similar to those reported in the capture of the StratixIV architecture. | ||
| - For the inter-die connection, we multiply the L4 wire delay of SIV by the ratio of the inter-die connection delay to the L4 wire delay of the Koios benchmark. | ||
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| - **Architectures:** | ||
| - `3d_10x10_noc_base_stratixiv_up.xml` | ||
| - A 10x10 NoC mech is put on the base die. | ||
| - The upper die is SIV-like FPGA fabric. | ||
| - `3d_full_inter_die_stratixiv_arch.timing.xml` | ||
| - The architecture has two dice. | ||
| - Both dice are SIV-like FPGA fabric. | ||
| - All pins can cross die. | ||
| - `3d_full_OPIN_inter_die_stratixiv_arch.timing.xml` | ||
| - The architecture has two dice. | ||
| - Both dice are SIV-like FPGA fabric. | ||
| - Only OPINs can cross die. | ||
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| 3. **simple_arch:** | ||
| - Simple architectures primarily used for quick testing in the flow. | ||
| - The inter-die delay of architectures in this file is considered to be zero. | ||
| - Contains two dice and both have the simple fabric. | ||
| - All pins can cross die. | ||
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vtr_flow/arch/multi_die/k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml
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vtr_flow/arch/multi_die/k6FracN10LB_mem20K_complexDSP_customSB_22nm_OPINs.xml
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