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Sep 13, 2024
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4af1381
extended e_side structure to contain above layer and below layer to g…
saaramahmoudi Aug 3, 2023
a3393e9
refactor for loops with e_side as iterator to always use SIDES array
saaramahmoudi Aug 3, 2023
76f7419
refactor index_into_correct_chan for custom switchblocks
saaramahmoudi Aug 8, 2023
4ff0ed6
make format
saaramahmoudi Aug 8, 2023
81155d5
removed the update that will change rr_graph for 2d cases
saaramahmoudi Aug 8, 2023
2b93973
modified the functions to determine custom switch blocks locations ba…
saaramahmoudi Aug 8, 2023
17beb30
modified index_into_correct_chan to consider layers to index to the c…
saaramahmoudi Aug 8, 2023
08cf7e9
modified wireconnection parsing while using custom switchblocks with …
saaramahmoudi Aug 10, 2023
92ebe0f
added edges to connect track to track in different layers, no additio…
saaramahmoudi Aug 15, 2023
f00977f
factor out the get_switchblocks_edges function and connect two layers…
saaramahmoudi Aug 15, 2023
f31a5fa
make format
saaramahmoudi Aug 15, 2023
8cbfc30
updated parsing custom switchblocks architecture syntax to connect bo…
saaramahmoudi Aug 17, 2023
84a5763
Merge branch 'master' into 3d_track_to_track_conn
saaramahmoudi Aug 25, 2023
50fbfce
add extra nodes (CHANX) in switchblocks with length = 0
saaramahmoudi Aug 25, 2023
4dac4a5
make format
saaramahmoudi Aug 25, 2023
99a7f2a
Merge branch 'master' into 3d_track_to_track_conn
saaramahmoudi Aug 31, 2023
9c6c9ad
Merge branch 'master' into 3d_track_to_track_conn
saaramahmoudi Aug 31, 2023
3939af1
add extra nodes for track-to-track connections in rr graph
saaramahmoudi Sep 1, 2023
15be495
set node attributes for custom extra nodes added to rrgraph to suppor…
saaramahmoudi Sep 1, 2023
e71b4a5
make format
saaramahmoudi Sep 1, 2023
2fe5adf
added track-to_track edges to correct node index in rr_graph
saaramahmoudi Sep 1, 2023
93d6b31
changed the hash function for sb_conn_map to use vtr::hash_combine
saaramahmoudi Sep 1, 2023
0891ca8
factor out counting extra nodes
saaramahmoudi Sep 14, 2023
aa804c2
debug: chanx nodes should have been added by (y,x)
saaramahmoudi Sep 15, 2023
6ba6321
removed extra TODOs and uncomment check_rr_graph
saaramahmoudi Sep 15, 2023
b0b6f5d
minor bug: offset to extra nodes was assigned to zero in the middle o…
saaramahmoudi Sep 15, 2023
eba99d2
update rr_graph serializer to have NONE as direction for extra chanx …
saaramahmoudi Sep 15, 2023
e55ecc8
debug: memory leak in rr_node_indices_ fixed
saaramahmoudi Sep 21, 2023
4e8580c
make format
saaramahmoudi Sep 21, 2023
c89ccf2
merge with master branch - conflicts solved
saaramahmoudi Sep 21, 2023
1d5eb35
generate_rr_graph_serializer
saaramahmoudi Sep 21, 2023
96aed46
resolved conflicts
saaramahmoudi Sep 21, 2023
f0d29f1
add support to read back rr graph with NONE direction CHANX nodes
saaramahmoudi Sep 21, 2023
6e44ce0
add one extra node per one destination in each switchblocks
saaramahmoudi Oct 4, 2023
830965c
debug: extra nodes was calculated incorrectly
saaramahmoudi Oct 5, 2023
45b890b
avoid adding same edge between chanx->chanx multiple times
saaramahmoudi Oct 5, 2023
17709bf
Merge branch 'master' of https://github.com/verilog-to-routing/vtr-ve…
saaramahmoudi Oct 5, 2023
5e12d1d
avoid adding same edge multiple times
saaramahmoudi Oct 9, 2023
91f016a
Merge branch 'master' of https://github.com/verilog-to-routing/vtr-ve…
saaramahmoudi Oct 9, 2023
1ada54e
fixed extra chanx connections between dice in rr graph
saaramahmoudi Oct 10, 2023
1370c03
removed unnecessary loop in the switchblocks pattern
saaramahmoudi Oct 19, 2023
b704e47
Merge branch '6d_router_lookahead' of https://github.com/verilog-to-r…
saaramahmoudi Oct 25, 2023
a4f452f
Merge branch 'master' of https://github.com/verilog-to-routing/vtr-ve…
saaramahmoudi Nov 29, 2023
58631f6
refactor switch blocks sides
saaramahmoudi Nov 29, 2023
5e2d636
update functions comments to be doxygen and remove duplicated comments
saaramahmoudi Nov 30, 2023
5a0b6d7
refactoring custom switchblocks functions
saaramahmoudi Nov 30, 2023
b275f1f
renaming the switch block 2D and 3D side variables
saaramahmoudi Nov 30, 2023
31e75dd
commented custom 3d switchblocks structs
saaramahmoudi Nov 30, 2023
a68257a
changed the function argument from pass by value to pass by ref const
saaramahmoudi Nov 30, 2023
626824d
commented rrgraph functions and extra nodes for 3D custom switchblocks
saaramahmoudi Nov 30, 2023
bf4f1c2
comment 3d custom switch block rrgraph-related functions
saaramahmoudi Nov 30, 2023
f7e6620
make format
saaramahmoudi Nov 30, 2023
56c9fd5
minor debug: total 3d array length and coords_out_of_bounds was incor…
saaramahmoudi Dec 4, 2023
59f5bd5
revert back index_into_correct_chan to return a single chanx/chany fo…
saaramahmoudi Dec 4, 2023
cf52ff2
modified index_into_correct_chan to use chanx/chany based on src side…
saaramahmoudi Dec 4, 2023
3208266
Merge branch 'master' of https://github.com/verilog-to-routing/vtr-ve…
saaramahmoudi Dec 4, 2023
8fb915d
Merge branch 'debug_6d_router_lookahead' of https://github.com/verilo…
saaramahmoudi Dec 4, 2023
e7f0629
added a new 3D architecture file with only inter-die connections in SBs
saaramahmoudi Dec 4, 2023
c78fc92
removed extra pinlocations tag within the 3D SB arch file
saaramahmoudi Dec 4, 2023
f274fbc
make format
saaramahmoudi Dec 4, 2023
c46aec0
removed duplicated code by making a helper function
saaramahmoudi Dec 5, 2023
18b2c5c
fixed switch id between 3D SB edges
saaramahmoudi Dec 5, 2023
0ac347b
make format
saaramahmoudi Dec 5, 2023
5326869
Merge branch 'master' into 3d_track_to_track_conn
saaramahmoudi Dec 6, 2023
c31ea65
vpr: set bounding box to net bounding box for high fanout nets
amin1377 Dec 8, 2023
c83fb79
Merge branch '3d_track_to_track_conn' of https://github.com/verilog-t…
amin1377 Dec 8, 2023
87f57cf
Merge branch 'master' into 3d_track_to_track_conn
saaramahmoudi Dec 10, 2023
630d731
return length 0 for extra chanx nodes
saaramahmoudi Dec 13, 2023
256ce68
assign delayless switch to extra rr edges created for 3D custom SBs
saaramahmoudi Dec 19, 2023
4684ed5
Merge branch 'master' into 3d_track_to_track_conn
saaramahmoudi Dec 19, 2023
d32c95b
vpr: placement experiment: remove src block for per-layer bounding box
amin1377 Dec 19, 2023
898d6f5
vpr: placer experiment: time delay profiler
amin1377 Dec 20, 2023
e4c9c96
vpr: placer experiment: turn on router debugger in delay profiling
amin1377 Dec 20, 2023
562f8cf
vpr: placer experiment: make the placer delay lookahead a 4D array
amin1377 Dec 21, 2023
41ae52c
vpr: placer experiment: update capnp proto with the new format
amin1377 Dec 21, 2023
54f28ce
vpr: placer experiment: update place lookahead dump with the new format
amin1377 Dec 21, 2023
68d4316
vpr: placer profiler: fix the index of sampling locations
amin1377 Dec 21, 2023
44fb542
vpr: placer profiler: fix the debugger sink node
amin1377 Dec 21, 2023
2e62d56
vpr: placer profiler: fix the loop boundries of sampling matrix
amin1377 Dec 21, 2023
fe072b8
vpr: placer lookup: add layer num to warning message
amin1377 Dec 21, 2023
886c55a
Merge branch 'simple_place_delay_model' of https://github.com/verilog…
amin1377 Dec 21, 2023
cf09b6a
Merge branch 'simple_place_delay_model' of https://github.com/verilog…
amin1377 Dec 21, 2023
7233203
Merge branch 'simple_place_delay_model' of https://github.com/verilog…
amin1377 Dec 22, 2023
071b529
Merge branch 'simple_place_delay_model' of https://github.com/verilog…
amin1377 Jan 5, 2024
760b5a0
vpr: place: add chanz_place_cost_fac which will be used by net_cost f…
amin1377 Apr 3, 2024
bcc7ca5
vpr: place: use chanz cost to cube bounding box cost
amin1377 Apr 3, 2024
1c10e7d
vpr: place: initialize chanz_place_cost_fac
amin1377 Apr 3, 2024
36ceeca
vpr: place: pass num_sink_per_layer to get_net_cost
amin1377 Apr 3, 2024
445e6d0
vpr: place: update layer min/max when cube bounding box is used
amin1377 Apr 3, 2024
240ae79
Merge branch 'bounding_box_3d_height' of https://github.com/verilog-t…
amin1377 Apr 3, 2024
d439ff8
vpr: place: base chanz_place_cost_fac on the average number of inter-…
amin1377 Apr 3, 2024
70c0645
Merge branch 'bounding_box_3d_height' of https://github.com/verilog-t…
amin1377 Apr 3, 2024
f46a775
Merge branch 'master' of https://github.com/verilog-to-routing/vtr-ve…
saaramahmoudi Apr 19, 2024
a3a3599
only resize the 3D SB matrix if it is being used
saaramahmoudi Apr 19, 2024
1309a04
Merge branch 'master' into 3d_track_to_track_conn
saaramahmoudi May 19, 2024
6ede692
added support for fan-out for intermediate nodes in 3D custom switchb…
saaramahmoudi May 20, 2024
006675f
removed dead code and added the command line option to control 3D cus…
saaramahmoudi May 20, 2024
620fd73
[vpr][router] print layer num of to block
amin1377 May 29, 2024
a38913c
Merge branch 'master' of https://github.com/verilog-to-routing/vtr-ve…
amin1377 Aug 14, 2024
792c276
[git] add .cache to git ignore
amin1377 Aug 14, 2024
377aed4
[log] fix printing location for 3d loc
amin1377 Aug 14, 2024
832d967
[vpr][route] print net num in log msg
amin1377 Aug 16, 2024
8a7a330
[test][strong] add strong 3d graph
amin1377 Aug 16, 2024
a909cf2
Merge branch 'master' of https://github.com/verilog-to-routing/vtr-ve…
amin1377 Aug 27, 2024
174bb0f
[vpr][route] fix seg fault when router debug is enabled
amin1377 Aug 29, 2024
1cebe67
Merge branch 'master' of https://github.com/verilog-to-routing/vtr-ve…
amin1377 Sep 9, 2024
c078262
[vpr][route] add all route tree nodes if no node from the target laye…
amin1377 Sep 9, 2024
b681f8d
[vpr][base] fix the bug with format coordinate (3d)
amin1377 Sep 12, 2024
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1 change: 1 addition & 0 deletions vpr/src/base/SetupVPR.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -481,6 +481,7 @@ static void SetupRouterOpts(const t_options& Options, t_router_opts* RouterOpts)
RouterOpts->generate_rr_node_overuse_report = Options.generate_rr_node_overuse_report;
RouterOpts->flat_routing = Options.flat_routing;
RouterOpts->has_choking_spot = Options.has_choking_spot;
RouterOpts->custom_3d_sb_fanin_fanout = Options.custom_3d_sb_fanin_fanout;
RouterOpts->with_timing_analysis = Options.timing_analysis;
}

Expand Down
7 changes: 7 additions & 0 deletions vpr/src/base/read_options.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -2461,6 +2461,13 @@ argparse::ArgumentParser create_arg_parser(const std::string& prog_name, t_optio
.default_value("false")
.show_in(argparse::ShowIn::HELP_ONLY);

route_grp.add_argument(args.custom_3d_sb_fanin_fanout, "--custom_3d_sb_fanin_fanout")
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This seems like it would fit better in the arch file (as a new parameter) than as a command line parameter. What do you think?

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I also think that it might be better to put it in the architecture file, but for now I just keep it as it is to make the testing easier with command line option. When the branch is final, I will talk to you about the architecture change.

.help(
"Specifies the number of tracks that can drive a 3D switch block connection"
"and the number of tracks that can be driven by a 3D switch block connection")
.default_value("1")
.show_in(argparse::ShowIn::HELP_ONLY);

auto& route_timing_grp = parser.add_argument_group("timing-driven routing options");

route_timing_grp.add_argument(args.astar_fac, "--astar_fac")
Expand Down
1 change: 1 addition & 0 deletions vpr/src/base/read_options.h
Original file line number Diff line number Diff line change
Expand Up @@ -202,6 +202,7 @@ struct t_options {
argparse::ArgValue<int> reorder_rr_graph_nodes_seed;
argparse::ArgValue<bool> flat_routing;
argparse::ArgValue<bool> has_choking_spot;
argparse::ArgValue<int> custom_3d_sb_fanin_fanout;

/* Timing-driven router options only */
argparse::ArgValue<float> astar_fac;
Expand Down
2 changes: 2 additions & 0 deletions vpr/src/base/vpr_types.h
Original file line number Diff line number Diff line change
Expand Up @@ -1464,6 +1464,8 @@ struct t_router_opts {
bool flat_routing;
bool has_choking_spot;

int custom_3d_sb_fanin_fanout = 1;

bool with_timing_analysis;

// Options related to rr_node reordering, for testing and possible cache optimization
Expand Down
14 changes: 0 additions & 14 deletions vpr/src/route/build_switchblocks.h
Original file line number Diff line number Diff line change
Expand Up @@ -92,20 +92,6 @@ struct t_switchblock_edge {
short to_wire_layer;
};

/**
* @brief contains the required information to create extra length-0 RR nodes to model 3D custom switch blocks connections within the RR graph
*
* @from_tracks a vector containing source tracks ptc_num indices that are connected to the same destination track in above or below layer in multi-die FPGAs
* @offset_to_extra_chanx_node index (max_chan_width + "offset_to_extra_chanx_node") to the correct length-0 RR node that all tracks in "from_tracks" should be connected to in RR graph.
* @connected_to_dest this flag is used to avoid edge duplications while adding edges for all "from_tracks" RR nodes to the same node (length-0 RR node) in the destination layer
*
*/
struct t_inter_die_switchblock_edge {
std::vector<short> from_tracks;
short offset_to_extra_chanx_node = -1;
bool connected_to_dest = false;
};

/* Switchblock connections are made as [x][y][from_side][to_side][from_wire_ind].
* The Switchblock_Lookup class specifies these dimensions.
* Furthermore, a source_wire at a given 5-d coordinate may connect to multiple destination wires so the value
Expand Down
18 changes: 14 additions & 4 deletions vpr/src/route/rr_graph.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -198,6 +198,7 @@ static std::function<void(t_chan_width*)> alloc_and_load_rr_graph(RRGraphBuilder
const t_chan_width& chan_width,
const int wire_to_ipin_switch,
const int wire_to_pin_between_dice_switch,
const int custom_3d_sb_fanin_fanout,
const int delayless_switch,
const enum e_directionality directionality,
bool* Fc_clipped,
Expand Down Expand Up @@ -482,6 +483,7 @@ static void build_rr_chan(RRGraphBuilder& rr_graph_builder,
t_rr_edge_info_set& des_3d_rr_edges_to_create,
const int wire_to_ipin_switch,
const int wire_to_pin_between_dice_switch,
const int custom_3d_sb_fanin_fanout,
const int delayless_switch,
const enum e_directionality directionality);

Expand Down Expand Up @@ -654,6 +656,7 @@ static void build_rr_graph(const t_graph_type graph_type,
const int global_route_switch,
const int wire_to_arch_ipin_switch,
const int wire_to_pin_between_dice_switch,
const int custom_3d_sb_fanin_fanout,
const int delayless_switch,
const float R_minW_nmos,
const float R_minW_pmos,
Expand Down Expand Up @@ -749,6 +752,7 @@ void create_rr_graph(const t_graph_type graph_type,
det_routing_arch->global_route_switch,
det_routing_arch->wire_to_arch_ipin_switch,
det_routing_arch->wire_to_arch_ipin_switch_between_dice,
router_opts.custom_3d_sb_fanin_fanout,
det_routing_arch->delayless_switch,
det_routing_arch->R_minW_nmos,
det_routing_arch->R_minW_pmos,
Expand Down Expand Up @@ -970,6 +974,7 @@ static void build_rr_graph(const t_graph_type graph_type,
const int global_route_switch,
const int wire_to_arch_ipin_switch,
const int wire_to_pin_between_dice_switch,
const int custom_3d_sb_fanin_fanout,
const int delayless_switch,
const float R_minW_nmos,
const float R_minW_pmos,
Expand Down Expand Up @@ -1271,7 +1276,7 @@ static void build_rr_graph(const t_graph_type graph_type,
*/
if (grid.get_num_layers() > 1 && sb_type == CUSTOM) {
//keep how many nodes each switchblock requires for each x,y location
auto extra_nodes_per_switchblock = get_number_track_to_track_inter_die_conn(sb_conn_map, device_ctx.rr_graph_builder);
auto extra_nodes_per_switchblock = get_number_track_to_track_inter_die_conn(sb_conn_map,custom_3d_sb_fanin_fanout, device_ctx.rr_graph_builder);
//allocate new nodes in each switchblocks
alloc_and_load_inter_die_rr_node_indices(device_ctx.rr_graph_builder, &nodes_per_chan, grid, extra_nodes_per_switchblock, &num_rr_nodes);
device_ctx.rr_graph_builder.resize_nodes(num_rr_nodes);
Expand Down Expand Up @@ -1371,6 +1376,7 @@ static void build_rr_graph(const t_graph_type graph_type,
nodes_per_chan,
wire_to_arch_ipin_switch,
wire_to_pin_between_dice_switch,
custom_3d_sb_fanin_fanout,
delayless_switch,
directionality,
&Fc_clipped,
Expand Down Expand Up @@ -2034,6 +2040,7 @@ static std::function<void(t_chan_width*)> alloc_and_load_rr_graph(RRGraphBuilder
const t_chan_width& chan_width,
const int wire_to_ipin_switch,
const int wire_to_pin_between_dice_switch,
const int custom_3d_sb_fanin_fanout,
const int delayless_switch,
const enum e_directionality directionality,
bool* Fc_clipped,
Expand Down Expand Up @@ -2186,6 +2193,7 @@ static std::function<void(t_chan_width*)> alloc_and_load_rr_graph(RRGraphBuilder
rr_edges_to_create, des_3d_rr_edges_to_create,
wire_to_ipin_switch,
wire_to_pin_between_dice_switch,
custom_3d_sb_fanin_fanout,
delayless_switch,
directionality);

Expand All @@ -2206,6 +2214,7 @@ static std::function<void(t_chan_width*)> alloc_and_load_rr_graph(RRGraphBuilder
rr_edges_to_create, des_3d_rr_edges_to_create,
wire_to_ipin_switch,
wire_to_pin_between_dice_switch,
custom_3d_sb_fanin_fanout,
delayless_switch,
directionality);

Expand Down Expand Up @@ -3115,6 +3124,7 @@ static void build_rr_chan(RRGraphBuilder& rr_graph_builder,
t_rr_edge_info_set& des_3d_rr_edges_to_create,
const int wire_to_ipin_switch,
const int wire_to_pin_between_dice_switch,
const int custom_3d_sb_fanin_fanout,
const int delayless_switch,
const enum e_directionality directionality) {
/* this function builds both x and y-directed channel segments, so set up our
Expand Down Expand Up @@ -3198,7 +3208,7 @@ static void build_rr_chan(RRGraphBuilder& rr_graph_builder,
opposite_chan_type, seg_dimension, max_opposite_chan_width, grid,
Fs_per_side, sblock_pattern, num_of_3d_conns_custom_SB, node, rr_edges_to_create,
des_3d_rr_edges_to_create, from_seg_details, to_seg_details, opposite_chan_details,
directionality,delayless_switch,
directionality,custom_3d_sb_fanin_fanout,delayless_switch,
switch_block_conn, sb_conn_map);
}
}
Expand All @@ -3218,7 +3228,7 @@ static void build_rr_chan(RRGraphBuilder& rr_graph_builder,
opposite_chan_type, seg_dimension, max_opposite_chan_width, grid,
Fs_per_side, sblock_pattern, num_of_3d_conns_custom_SB, node, rr_edges_to_create,
des_3d_rr_edges_to_create, from_seg_details, to_seg_details, opposite_chan_details,
directionality, delayless_switch, switch_block_conn, sb_conn_map);
directionality,custom_3d_sb_fanin_fanout, delayless_switch, switch_block_conn, sb_conn_map);
}
}

Expand Down Expand Up @@ -3250,7 +3260,7 @@ static void build_rr_chan(RRGraphBuilder& rr_graph_builder,
chan_type, seg_dimension, max_chan_width, grid,
Fs_per_side, sblock_pattern, num_of_3d_conns_custom_SB, node, rr_edges_to_create,
des_3d_rr_edges_to_create, from_seg_details, to_seg_details, from_chan_details,
directionality,delayless_switch,
directionality,custom_3d_sb_fanin_fanout, delayless_switch,
switch_block_conn, sb_conn_map);
}
}
Expand Down
18 changes: 13 additions & 5 deletions vpr/src/route/rr_graph2.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -126,6 +126,7 @@ static void get_switchblocks_edges(RRGraphBuilder& rr_graph_builder,
const int to_y,
const t_rr_type to_chan_type,
const int switch_override,
const int custom_3d_sb_fanin_fanout,
const int delayless_switch,
t_sb_connection_map* sb_conn_map,
vtr::NdMatrix<int, 2>& num_of_3d_conns_custom_SB,
Expand Down Expand Up @@ -163,6 +164,7 @@ static int get_track_to_chan_seg(RRGraphBuilder& rr_graph_builder,
const e_side from_side,
const e_side to_side,
const int swtich_override,
const int custom_3d_sb_fanin_fanout,
const int delayless_switch,
t_sb_connection_map* sb_conn_map,
vtr::NdMatrix<int, 2>& num_of_3d_conns_custom_SB,
Expand Down Expand Up @@ -1245,6 +1247,7 @@ static bool check_3d_SB_RRnodes(RRGraphBuilder& rr_graph_builder, int x, int y,
}

vtr::NdMatrix<int, 2> get_number_track_to_track_inter_die_conn(t_sb_connection_map* sb_conn_map,
const int custom_3d_sb_fanin_fanout,
RRGraphBuilder& rr_graph_builder) {
auto& grid_ctx = g_vpr_ctx.device().grid;
vtr::NdMatrix<int, 2> extra_nodes_per_switchblocks;
Expand Down Expand Up @@ -1283,7 +1286,7 @@ vtr::NdMatrix<int, 2> get_number_track_to_track_inter_die_conn(t_sb_connection_m
}
}
}
extra_nodes_per_switchblocks[x][y] += ((num_of_3d_conn + 39)/ 40);
extra_nodes_per_switchblocks[x][y] += ((num_of_3d_conn + custom_3d_sb_fanin_fanout - 1)/ custom_3d_sb_fanin_fanout);
}
}
}
Expand Down Expand Up @@ -1924,6 +1927,7 @@ int get_track_to_tracks(RRGraphBuilder& rr_graph_builder,
const t_chan_seg_details* to_seg_details,
const t_chan_details& to_chan_details,
const enum e_directionality directionality,
const int custom_3d_sb_fanin_fanout,
const int delayless_switch,
const vtr::NdMatrix<std::vector<int>, 3>& switch_block_conn,
t_sb_connection_map* sb_conn_map) {
Expand Down Expand Up @@ -2056,7 +2060,7 @@ int get_track_to_tracks(RRGraphBuilder& rr_graph_builder,
if (Direction::DEC == from_seg_details[from_track].direction() || BI_DIRECTIONAL == directionality) {
num_conn += get_track_to_chan_seg(rr_graph_builder, layer, max_chan_width, from_track, to_chan, to_seg,
to_type, from_side_a, to_side,
switch_override, delayless_switch,
switch_override, custom_3d_sb_fanin_fanout, delayless_switch,
sb_conn_map, num_of_3d_conns_custom_SB, from_rr_node, rr_edges_to_create, des_3d_rr_edges_to_create);
}
} else {
Expand Down Expand Up @@ -2094,7 +2098,7 @@ int get_track_to_tracks(RRGraphBuilder& rr_graph_builder,
if (Direction::INC == from_seg_details[from_track].direction() || BI_DIRECTIONAL == directionality) {
num_conn += get_track_to_chan_seg(rr_graph_builder, layer, max_chan_width, from_track, to_chan, to_seg,
to_type, from_side_b, to_side,
switch_override,delayless_switch,
switch_override,custom_3d_sb_fanin_fanout, delayless_switch,
sb_conn_map, num_of_3d_conns_custom_SB, from_rr_node, rr_edges_to_create, des_3d_rr_edges_to_create);
}
} else {
Expand Down Expand Up @@ -2240,6 +2244,7 @@ static void get_switchblocks_edges(RRGraphBuilder& rr_graph_builder,
const int to_y,
const t_rr_type to_chan_type,
const int switch_override,
const int custom_3d_sb_fanin_fanout,
const int delayless_switch,
t_sb_connection_map* sb_conn_map,
vtr::NdMatrix<int, 2>& num_of_3d_conns_custom_SB,
Expand Down Expand Up @@ -2309,7 +2314,7 @@ static void get_switchblocks_edges(RRGraphBuilder& rr_graph_builder,
* +-------------+ +-------------+ +--------------+ +--------------+
*
* */
int offset = num_of_3d_conns_custom_SB[tile_x][tile_y] / 40;
int offset = num_of_3d_conns_custom_SB[tile_x][tile_y] / custom_3d_sb_fanin_fanout;
RRNodeId track_to_chanx_node = rr_graph_builder.node_lookup().find_node(layer, tile_x, tile_y, CHANX, max_chan_width + offset);
RRNodeId diff_layer_chanx_node = rr_graph_builder.node_lookup().find_node(to_layer, tile_x, tile_y, CHANX, max_chan_width + offset);
RRNodeId chanx_to_track_node = rr_graph_builder.node_lookup().find_node(to_layer, to_x, to_y, to_chan_type, to_wire);
Expand All @@ -2333,7 +2338,7 @@ static void get_switchblocks_edges(RRGraphBuilder& rr_graph_builder,
++edge_count;

//we only add the following edge between intermediate nodes once for the first 3D connection for each pair of intermediate nodes
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Is there a big comment somewhere saying how custom_3d_sb_fanin_fanout works? It should detail exactly what the rr graph this generates looks like.

if (num_of_3d_conns_custom_SB[tile_x][tile_y] % 40 == 0) {
if (num_of_3d_conns_custom_SB[tile_x][tile_y] % custom_3d_sb_fanin_fanout == 0) {
rr_edges_to_create.emplace_back(track_to_chanx_node, diff_layer_chanx_node, delayless_switch, false);
++edge_count;
}
Expand All @@ -2354,6 +2359,7 @@ static int get_track_to_chan_seg(RRGraphBuilder& rr_graph_builder,
const e_side from_side,
const e_side to_side,
const int switch_override,
const int custom_3d_sb_fanin_fanout,
const int delayless_switch,
t_sb_connection_map* sb_conn_map,
vtr::NdMatrix<int, 2>& num_of_3d_conns_custom_SB,
Expand Down Expand Up @@ -2393,6 +2399,7 @@ static int get_track_to_chan_seg(RRGraphBuilder& rr_graph_builder,
to_y,
to_chan_type,
switch_override,
custom_3d_sb_fanin_fanout,
delayless_switch,
sb_conn_map,
num_of_3d_conns_custom_SB,
Expand All @@ -2415,6 +2422,7 @@ static int get_track_to_chan_seg(RRGraphBuilder& rr_graph_builder,
to_y,
to_chan_type,
switch_override,
custom_3d_sb_fanin_fanout,
delayless_switch,
sb_conn_map,
num_of_3d_conns_custom_SB,
Expand Down
2 changes: 2 additions & 0 deletions vpr/src/route/rr_graph2.h
Original file line number Diff line number Diff line change
Expand Up @@ -87,6 +87,7 @@ int get_rr_node_index(const t_rr_node_indices& L_rr_node_indices,
* @return number of die-crossing connection for each unique (x, y) location within the grid ([0..grid.width-1][0..grid.height-1])
*/
vtr::NdMatrix<int, 2> get_number_track_to_track_inter_die_conn(t_sb_connection_map* sb_conn_map,
const int custom_3d_sb_fanin_fanout,
RRGraphBuilder& rr_graph_builder);

int find_average_rr_node_index(int device_width,
Expand Down Expand Up @@ -216,6 +217,7 @@ int get_track_to_tracks(RRGraphBuilder& rr_graph_builder,
const t_chan_seg_details* to_seg_details,
const t_chan_details& to_chan_details,
const enum e_directionality directionality,
const int custom_3d_sb_fanin_fanout,
const int delayless_switch,
const vtr::NdMatrix<std::vector<int>, 3>& switch_block_conn,
t_sb_connection_map* sb_conn_map);
Expand Down
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